1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics STM32 USB HS PHY controller binding 8 9description: 10 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 12 switch. It controls PHY configuration and status, and the UTMI+ switch that 13 selects either OTG or HOST controller for the second PHY port. It also sets 14 PLL configuration. 15 16 USBPHYC 17 |_ PLL 18 | 19 |_ PHY port#1 _________________ HOST controller 20 | __ | 21 | / 1|________________| 22 |_ PHY port#2 ----| |________________ 23 | \_0| | 24 |_ UTMI switch_______| OTG controller 25 26maintainers: 27 - Amelie Delaunay <amelie.delaunay@foss.st.com> 28 29properties: 30 compatible: 31 const: st,stm32mp1-usbphyc 32 33 reg: 34 maxItems: 1 35 36 clocks: 37 maxItems: 1 38 39 resets: 40 maxItems: 1 41 42 "#address-cells": 43 const: 1 44 45 "#size-cells": 46 const: 0 47 48 vdda1v1-supply: 49 description: regulator providing 1V1 power supply to the PLL block 50 51 vdda1v8-supply: 52 description: regulator providing 1V8 power supply to the PLL block 53 54 '#clock-cells': 55 description: number of clock cells for ck_usbo_48m consumer 56 const: 0 57 58#Required child nodes: 59 60patternProperties: 61 "^usb-phy@[0|1]$": 62 type: object 63 description: 64 Each port the controller provides must be represented as a sub-node. 65 66 properties: 67 reg: 68 description: phy port index. 69 maxItems: 1 70 71 phy-supply: 72 description: regulator providing 3V3 power supply to the PHY. 73 74 "#phy-cells": 75 enum: [ 0x0, 0x1 ] 76 77 connector: 78 type: object 79 $ref: /schemas/connector/usb-connector.yaml 80 properties: 81 vbus-supply: true 82 83 # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due 84 # to USB connector/receptacle, routing, ESD protection component,... Here is the list of 85 # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- 86 # Speed, LS for Low-Speed) 87 88 st,current-boost-microamp: 89 description: Current boosting in uA 90 enum: [ 1000, 2000 ] 91 92 st,no-lsfs-fb-cap: 93 description: Disables the LS/FS feedback capacitor 94 type: boolean 95 96 st,decrease-hs-slew-rate: 97 description: Decreases the HS driver slew rate by 10% 98 type: boolean 99 100 st,tune-hs-dc-level: 101 description: | 102 Tunes the HS driver DC level 103 - <0> normal level 104 - <1> increases the level by 5 to 7 mV 105 - <2> increases the level by 10 to 14 mV 106 - <3> decreases the level by 5 to 7 mV 107 $ref: /schemas/types.yaml#/definitions/uint32 108 minimum: 0 109 maximum: 3 110 default: 0 111 112 st,enable-fs-rftime-tuning: 113 description: Enables the FS rise/fall tuning option 114 type: boolean 115 116 st,enable-hs-rftime-reduction: 117 description: Enables the HS rise/fall reduction feature 118 type: boolean 119 120 st,trim-hs-current: 121 description: | 122 Controls HS driver current trimming for choke compensation 123 - <0> = 18.87 mA target current / nominal + 0% 124 - <1> = 19.165 mA target current / nominal + 1.56% 125 - <2> = 19.46 mA target current / nominal + 3.12% 126 - <3> = 19.755 mA target current / nominal + 4.68% 127 - <4> = 20.05 mA target current / nominal + 6.24% 128 - <5> = 20.345 mA target current / nominal + 7.8% 129 - <6> = 20.64 mA target current / nominal + 9.36% 130 - <7> = 20.935 mA target current / nominal + 10.92% 131 - <8> = 21.23 mA target current / nominal + 12.48% 132 - <9> = 21.525 mA target current / nominal + 14.04% 133 - <10> = 21.82 mA target current / nominal + 15.6% 134 - <11> = 22.115 mA target current / nominal + 17.16% 135 - <12> = 22.458 mA target current / nominal + 19.01% 136 - <13> = 22.755 mA target current / nominal + 20.58% 137 - <14> = 23.052 mA target current / nominal + 22.16% 138 - <15> = 23.348 mA target current / nominal + 23.73% 139 $ref: /schemas/types.yaml#/definitions/uint32 140 minimum: 0 141 maximum: 15 142 default: 0 143 144 st,trim-hs-impedance: 145 description: | 146 Controls HS driver impedance tuning for choke compensation 147 - <0> = no impedance offset 148 - <1> = reduce the impedance by 2 ohms 149 - <2> = reduce the impedance by 4 ohms 150 - <3> = reduce the impedance by 6 ohms 151 $ref: /schemas/types.yaml#/definitions/uint32 152 minimum: 0 153 maximum: 3 154 default: 0 155 156 st,tune-squelch-level: 157 description: | 158 Tunes the squelch DC threshold value 159 - <0> = no shift in threshold 160 - <1> = threshold shift by +7 mV 161 - <2> = threshold shift by -5 mV 162 - <3> = threshold shift by +14 mV 163 $ref: /schemas/types.yaml#/definitions/uint32 164 minimum: 0 165 maximum: 3 166 default: 0 167 168 st,enable-hs-rx-gain-eq: 169 description: Enables the HS Rx gain equalizer 170 type: boolean 171 172 st,tune-hs-rx-offset: 173 description: | 174 Adjusts the HS Rx offset 175 - <0> = no offset 176 - <1> = offset of +5 mV 177 - <2> = offset of +10 mV 178 - <3> = offset of -5 mV 179 $ref: /schemas/types.yaml#/definitions/uint32 180 minimum: 0 181 maximum: 3 182 default: 0 183 184 st,no-hs-ftime-ctrl: 185 description: Disables the HS fall time control of single ended signals during pre-emphasis 186 type: boolean 187 188 st,no-lsfs-sc: 189 description: Disables the short circuit protection in LS/FS driver 190 type: boolean 191 192 st,enable-hs-tx-staggering: 193 description: Enables the basic staggering in HS Tx mode 194 type: boolean 195 196 allOf: 197 - if: 198 properties: 199 reg: 200 const: 0 201 then: 202 properties: 203 "#phy-cells": 204 const: 0 205 else: 206 properties: 207 "#phy-cells": 208 const: 1 209 description: 210 The value is used to select UTMI switch output. 211 0 for OTG controller and 1 for Host controller. 212 213 required: 214 - reg 215 - phy-supply 216 - "#phy-cells" 217 218 additionalProperties: false 219 220required: 221 - compatible 222 - reg 223 - clocks 224 - "#address-cells" 225 - "#size-cells" 226 - vdda1v1-supply 227 - vdda1v8-supply 228 - usb-phy@0 229 - usb-phy@1 230 231additionalProperties: false 232 233examples: 234 - | 235 #include <dt-bindings/clock/stm32mp1-clks.h> 236 #include <dt-bindings/reset/stm32mp1-resets.h> 237 usbphyc: usbphyc@5a006000 { 238 compatible = "st,stm32mp1-usbphyc"; 239 reg = <0x5a006000 0x1000>; 240 clocks = <&rcc USBPHY_K>; 241 resets = <&rcc USBPHY_R>; 242 vdda1v1-supply = <®11>; 243 vdda1v8-supply = <®18>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 #clock-cells = <0>; 247 248 usbphyc_port0: usb-phy@0 { 249 reg = <0>; 250 phy-supply = <&vdd_usb>; 251 #phy-cells = <0>; 252 st,tune-hs-dc-level = <2>; 253 st,enable-fs-rftime-tuning; 254 st,enable-hs-rftime-reduction; 255 st,trim-hs-current = <15>; 256 st,trim-hs-impedance = <1>; 257 st,tune-squelch-level = <3>; 258 st,tune-hs-rx-offset = <2>; 259 st,no-lsfs-sc; 260 connector { 261 compatible = "usb-a-connector"; 262 vbus-supply = <&vbus_sw>; 263 }; 264 }; 265 266 usbphyc_port1: usb-phy@1 { 267 reg = <1>; 268 phy-supply = <&vdd_usb>; 269 #phy-cells = <1>; 270 st,tune-hs-dc-level = <2>; 271 st,enable-fs-rftime-tuning; 272 st,enable-hs-rftime-reduction; 273 st,trim-hs-current = <15>; 274 st,trim-hs-impedance = <1>; 275 st,tune-squelch-level = <3>; 276 st,tune-hs-rx-offset = <2>; 277 st,no-lsfs-sc; 278 }; 279 }; 280... 281