1STMicroelectronics STM32 USB HS PHY controller 2 3The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 4switch. It controls PHY configuration and status, and the UTMI+ switch that 5selects either OTG or HOST controller for the second PHY port. It also sets 6PLL configuration. 7 8USBPHYC 9 |_ PLL 10 | 11 |_ PHY port#1 _________________ HOST controller 12 | _ | 13 | / 1|________________| 14 |_ PHY port#2 ----| |________________ 15 | \_0| | 16 |_ UTMI switch_______| OTG controller 17 18 19Phy provider node 20================= 21 22Required properties: 23- compatible: must be "st,stm32mp1-usbphyc" 24- reg: address and length of the usb phy control register set 25- clocks: phandle + clock specifier for the PLL phy clock 26- #address-cells: number of address cells for phys sub-nodes, must be <1> 27- #size-cells: number of size cells for phys sub-nodes, must be <0> 28 29Optional properties: 30- assigned-clocks: phandle + clock specifier for the PLL phy clock 31- assigned-clock-parents: the PLL phy clock parent 32- resets: phandle + reset specifier 33 34Required nodes: one sub-node per port the controller provides. 35 36Phy sub-nodes 37============== 38 39Required properties: 40- reg: phy port index 41- phy-supply: phandle to the regulator providing 3V3 power to the PHY, 42 see phy-bindings.txt in the same directory. 43- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY 44- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY 45- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY 46 port#1 and must be <1> for PHY port#2, to select USB controller 47 48 49Example: 50 usbphyc: usb-phy@5a006000 { 51 compatible = "st,stm32mp1-usbphyc"; 52 reg = <0x5a006000 0x1000>; 53 clocks = <&rcc_clk USBPHY_K>; 54 resets = <&rcc_rst USBPHY_R>; 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 usbphyc_port0: usb-phy@0 { 59 reg = <0>; 60 phy-supply = <&vdd_usb>; 61 vdda1v1-supply = <®11>; 62 vdda1v8-supply = <®18> 63 #phy-cells = <0>; 64 }; 65 66 usbphyc_port1: usb-phy@1 { 67 reg = <1>; 68 phy-supply = <&vdd_usb>; 69 vdda1v1-supply = <®11>; 70 vdda1v8-supply = <®18> 71 #phy-cells = <1>; 72 }; 73 }; 74