xref: /freebsd/sys/contrib/device-tree/Bindings/phy/phy-rockchip-inno-usb2.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip USB2.0 phy with inno IP block
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,px30-usb2phy
16      - rockchip,rk3228-usb2phy
17      - rockchip,rk3308-usb2phy
18      - rockchip,rk3328-usb2phy
19      - rockchip,rk3366-usb2phy
20      - rockchip,rk3399-usb2phy
21      - rockchip,rk3568-usb2phy
22      - rockchip,rv1108-usb2phy
23
24  reg:
25    maxItems: 1
26
27  clock-output-names:
28    description:
29      The usb 480m output clock name.
30
31  "#clock-cells":
32    const: 0
33
34  clocks:
35    maxItems: 1
36
37  clock-names:
38    const: phyclk
39
40  assigned-clocks:
41    description:
42      Phandle of the usb 480m clock.
43
44  assigned-clock-parents:
45    description:
46      Parent of the usb 480m clock.
47      Select between usb-phy output 480m and xin24m.
48      Refer to clk/clock-bindings.txt for generic clock consumer properties.
49
50  extcon:
51    description:
52      Phandle to the extcon device providing the cable state for the otg phy.
53
54  interrupts:
55    description: Muxed interrupt for both ports
56    maxItems: 1
57
58  rockchip,usbgrf:
59    $ref: /schemas/types.yaml#/definitions/phandle
60    description:
61      Phandle to the syscon managing the 'usb general register files'.
62      When set the driver will request its phandle as one companion-grf
63      for some special SoCs (e.g rv1108).
64
65  host-port:
66    type: object
67    additionalProperties: false
68
69    properties:
70      "#phy-cells":
71        const: 0
72
73      interrupts:
74        description: host linestate interrupt
75        maxItems: 1
76
77      interrupt-names:
78        const: linestate
79
80      phy-supply:
81        description:
82          Phandle to a regulator that provides power to VBUS.
83          See ./phy-bindings.txt for details.
84
85    required:
86      - "#phy-cells"
87
88  otg-port:
89    type: object
90    additionalProperties: false
91
92    properties:
93      "#phy-cells":
94        const: 0
95
96      interrupts:
97        minItems: 1
98        maxItems: 3
99
100      interrupt-names:
101        oneOf:
102          - const: linestate
103          - const: otg-mux
104          - items:
105              - const: otg-bvalid
106              - const: otg-id
107              - const: linestate
108
109      phy-supply:
110        description:
111          Phandle to a regulator that provides power to VBUS.
112          See ./phy-bindings.txt for details.
113
114    required:
115      - "#phy-cells"
116
117required:
118  - compatible
119  - reg
120  - clock-output-names
121  - "#clock-cells"
122  - host-port
123  - otg-port
124
125allOf:
126  - if:
127      properties:
128        compatible:
129          contains:
130            const: rockchip,rk3568-usb2phy
131
132    then:
133      properties:
134        host-port:
135          properties:
136            interrupts: false
137
138        otg-port:
139          properties:
140            interrupts: false
141
142      required:
143        - interrupts
144
145    else:
146      properties:
147        interrupts: false
148
149        host-port:
150          required:
151            - interrupts
152            - interrupt-names
153
154        otg-port:
155          required:
156            - interrupts
157            - interrupt-names
158
159additionalProperties: false
160
161examples:
162  - |
163    #include <dt-bindings/clock/rk3399-cru.h>
164    #include <dt-bindings/interrupt-controller/arm-gic.h>
165    #include <dt-bindings/interrupt-controller/irq.h>
166    u2phy0: usb2phy@e450 {
167      compatible = "rockchip,rk3399-usb2phy";
168      reg = <0xe450 0x10>;
169      clocks = <&cru SCLK_USB2PHY0_REF>;
170      clock-names = "phyclk";
171      clock-output-names = "clk_usbphy0_480m";
172      #clock-cells = <0>;
173
174      u2phy0_host: host-port {
175        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
176        interrupt-names = "linestate";
177        #phy-cells = <0>;
178      };
179
180      u2phy0_otg: otg-port {
181        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
182                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
183                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
184        interrupt-names = "otg-bvalid", "otg-id", "linestate";
185        #phy-cells = <0>;
186      };
187    };
188