xref: /freebsd/sys/contrib/device-tree/Bindings/phy/phy-rockchip-inno-usb2.yaml (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip USB2.0 phy with inno IP block
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,px30-usb2phy
16      - rockchip,rk3228-usb2phy
17      - rockchip,rk3308-usb2phy
18      - rockchip,rk3328-usb2phy
19      - rockchip,rk3366-usb2phy
20      - rockchip,rk3399-usb2phy
21      - rockchip,rv1108-usb2phy
22
23  reg:
24    maxItems: 1
25
26  clock-output-names:
27    description:
28      The usb 480m output clock name.
29
30  "#clock-cells":
31    const: 0
32
33  clocks:
34    maxItems: 1
35
36  clock-names:
37    const: phyclk
38
39  assigned-clocks:
40    description:
41      Phandle of the usb 480m clock.
42
43  assigned-clock-parents:
44    description:
45      Parent of the usb 480m clock.
46      Select between usb-phy output 480m and xin24m.
47      Refer to clk/clock-bindings.txt for generic clock consumer properties.
48
49  extcon:
50    description:
51      Phandle to the extcon device providing the cable state for the otg phy.
52
53  rockchip,usbgrf:
54    $ref: /schemas/types.yaml#/definitions/phandle
55    description:
56      Phandle to the syscon managing the 'usb general register files'.
57      When set the driver will request its phandle as one companion-grf
58      for some special SoCs (e.g rv1108).
59
60  host-port:
61    type: object
62    additionalProperties: false
63
64    properties:
65      "#phy-cells":
66        const: 0
67
68      interrupts:
69        description: host linestate interrupt
70
71      interrupt-names:
72        const: linestate
73
74      phy-supply:
75        description:
76          Phandle to a regulator that provides power to VBUS.
77          See ./phy-bindings.txt for details.
78
79    required:
80      - "#phy-cells"
81      - interrupts
82      - interrupt-names
83
84  otg-port:
85    type: object
86    additionalProperties: false
87
88    properties:
89      "#phy-cells":
90        const: 0
91
92      interrupts:
93        minItems: 1
94        maxItems: 3
95
96      interrupt-names:
97        oneOf:
98          - const: linestate
99          - const: otg-mux
100          - items:
101              - const: otg-bvalid
102              - const: otg-id
103              - const: linestate
104
105      phy-supply:
106        description:
107          Phandle to a regulator that provides power to VBUS.
108          See ./phy-bindings.txt for details.
109
110    required:
111      - "#phy-cells"
112      - interrupts
113      - interrupt-names
114
115required:
116  - compatible
117  - reg
118  - clock-output-names
119  - "#clock-cells"
120  - host-port
121  - otg-port
122
123additionalProperties: false
124
125examples:
126  - |
127    #include <dt-bindings/clock/rk3399-cru.h>
128    #include <dt-bindings/interrupt-controller/arm-gic.h>
129    #include <dt-bindings/interrupt-controller/irq.h>
130    u2phy0: usb2phy@e450 {
131      compatible = "rockchip,rk3399-usb2phy";
132      reg = <0xe450 0x10>;
133      clocks = <&cru SCLK_USB2PHY0_REF>;
134      clock-names = "phyclk";
135      clock-output-names = "clk_usbphy0_480m";
136      #clock-cells = <0>;
137
138      u2phy0_host: host-port {
139        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
140        interrupt-names = "linestate";
141        #phy-cells = <0>;
142      };
143
144      u2phy0_otg: otg-port {
145        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
146                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
147                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
148        interrupt-names = "otg-bvalid", "otg-id", "linestate";
149        #phy-cells = <0>;
150      };
151    };
152