1MediaTek XS-PHY binding 2-------------------------- 3 4The XS-PHY controller supports physical layer functionality for USB3.1 5GEN2 controller on MediaTek SoCs. 6 7Required properties (controller (parent) node): 8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy", 9 soc-model is the name of SoC, such as mt3611 etc; 10 when using "mediatek,xsphy" compatible string, you need SoC specific 11 ones in addition, one of: 12 - "mediatek,mt3611-xsphy" 13 14 - #address-cells, #size-cells : should use the same values as the root node 15 - ranges: must be present 16 17Optional properties (controller (parent) node): 18 - reg : offset and length of register shared by multiple U3 ports, 19 exclude port's private register, if only U2 ports provided, 20 shouldn't use the property. 21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate 22 calibrate 23 - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on 24 SoC process 25 26Required nodes : a sub-node is required for each port the controller 27 provides. Address range information including the usual 28 'reg' property is used inside these nodes to describe 29 the controller's topology. 30 31Required properties (port (child) node): 32- reg : address and length of the register set for the port. 33- clocks : a list of phandle + clock-specifier pairs, one for each 34 entry in clock-names 35- clock-names : must contain 36 "ref": 48M reference clock for HighSpeed analog phy; and 26M 37 reference clock for SuperSpeedPlus analog phy, sometimes is 38 24M, 25M or 27M, depended on platform. 39- #phy-cells : should be 1 40 cell after port phandle is phy type from: 41 - PHY_TYPE_USB2 42 - PHY_TYPE_USB3 43 44The following optional properties are only for debug or HQA test 45Optional properties (PHY_TYPE_USB2 port (child) node): 46- mediatek,eye-src : u32, the value of slew rate calibrate 47- mediatek,eye-vrt : u32, the selection of VRT reference voltage 48- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage 49- mediatek,efuse-intr : u32, the selection of Internal Resistor 50 51Optional properties (PHY_TYPE_USB3 port (child) node): 52- mediatek,efuse-intr : u32, the selection of Internal Resistor 53- mediatek,efuse-tx-imp : u32, the selection of TX Impedance 54- mediatek,efuse-rx-imp : u32, the selection of RX Impedance 55 56Banks layout of xsphy 57------------------------------------------------------------- 58port offset bank 59u2 port0 0x0000 MISC 60 0x0100 FMREG 61 0x0300 U2PHY_COM 62u2 port1 0x1000 MISC 63 0x1100 FMREG 64 0x1300 U2PHY_COM 65u2 port2 0x2000 MISC 66 ... 67u31 common 0x3000 DIG_GLB 68 0x3100 PHYA_GLB 69u31 port0 0x3400 DIG_LN_TOP 70 0x3500 DIG_LN_TX0 71 0x3600 DIG_LN_RX0 72 0x3700 DIG_LN_DAIF 73 0x3800 PHYA_LN 74u31 port1 0x3a00 DIG_LN_TOP 75 0x3b00 DIG_LN_TX0 76 0x3c00 DIG_LN_RX0 77 0x3d00 DIG_LN_DAIF 78 0x3e00 PHYA_LN 79 ... 80 81DIG_GLB & PHYA_GLB are shared by U31 ports. 82 83Example: 84 85u3phy: usb-phy@11c40000 { 86 compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy"; 87 reg = <0 0x11c43000 0 0x0200>; 88 mediatek,src-ref-clk-mhz = <26>; 89 mediatek,src-coef = <17>; 90 #address-cells = <2>; 91 #size-cells = <2>; 92 ranges; 93 94 u2port0: usb-phy@11c40000 { 95 reg = <0 0x11c40000 0 0x0400>; 96 clocks = <&clk48m>; 97 clock-names = "ref"; 98 mediatek,eye-src = <4>; 99 #phy-cells = <1>; 100 }; 101 102 u3port0: usb-phy@11c43000 { 103 reg = <0 0x11c43400 0 0x0500>; 104 clocks = <&clk26m>; 105 clock-names = "ref"; 106 mediatek,efuse-intr = <28>; 107 #phy-cells = <1>; 108 }; 109}; 110