1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence Torrent SD0801 PHY 8 9description: 10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) 11 hardware included with the Cadence MHDP DisplayPort controller. Torrent 12 PHY also supports multilink multiprotocol combinations including protocols 13 such as PCIe, USB, SGMII, QSGMII etc. 14 15maintainers: 16 - Swapnil Jakhade <sjakhade@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com> 18 19properties: 20 compatible: 21 enum: 22 - cdns,torrent-phy 23 - ti,j721e-serdes-10g 24 25 '#address-cells': 26 const: 1 27 28 '#size-cells': 29 const: 0 30 31 '#clock-cells': 32 const: 1 33 34 clocks: 35 minItems: 1 36 maxItems: 2 37 description: 38 PHY reference clock for 1 item. Must contain an entry in clock-names. 39 Optional Parent to enable output reference clock. 40 41 clock-names: 42 minItems: 1 43 items: 44 - const: refclk 45 - const: phy_en_refclk 46 47 reg: 48 minItems: 1 49 items: 50 - description: Offset of the Torrent PHY configuration registers. 51 - description: Offset of the DPTX PHY configuration registers. 52 53 reg-names: 54 minItems: 1 55 items: 56 - const: torrent_phy 57 - const: dptx_phy 58 59 resets: 60 minItems: 1 61 items: 62 - description: Torrent PHY reset. 63 - description: Torrent APB reset. This is optional. 64 65 reset-names: 66 minItems: 1 67 items: 68 - const: torrent_reset 69 - const: torrent_apb 70 71patternProperties: 72 '^phy@[0-3]$': 73 type: object 74 description: 75 Each group of PHY lanes with a single master lane should be represented as a sub-node. 76 properties: 77 reg: 78 description: 79 The master lane number. This is the lowest numbered lane in the lane group. 80 minimum: 0 81 maximum: 3 82 83 resets: 84 minItems: 1 85 maxItems: 4 86 description: 87 Contains list of resets, one per lane, to get all the link lanes out of reset. 88 89 "#phy-cells": 90 const: 0 91 92 cdns,phy-type: 93 description: 94 Specifies the type of PHY for which the group of PHY lanes is used. 95 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. 96 $ref: /schemas/types.yaml#/definitions/uint32 97 minimum: 1 98 maximum: 9 99 100 cdns,num-lanes: 101 description: 102 Number of lanes. 103 $ref: /schemas/types.yaml#/definitions/uint32 104 enum: [1, 2, 3, 4] 105 default: 4 106 107 cdns,ssc-mode: 108 description: 109 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, 110 EXTERNAL_SSC or INTERNAL_SSC. 111 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used. 112 $ref: /schemas/types.yaml#/definitions/uint32 113 enum: [0, 1, 2] 114 default: 0 115 116 cdns,max-bit-rate: 117 description: 118 Maximum DisplayPort link bit rate to use, in Mbps 119 $ref: /schemas/types.yaml#/definitions/uint32 120 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] 121 default: 8100 122 123 required: 124 - reg 125 - resets 126 - "#phy-cells" 127 - cdns,phy-type 128 - cdns,num-lanes 129 130 additionalProperties: false 131 132required: 133 - compatible 134 - "#address-cells" 135 - "#size-cells" 136 - clocks 137 - clock-names 138 - reg 139 - reg-names 140 - resets 141 - reset-names 142 143additionalProperties: false 144 145examples: 146 - | 147 #include <dt-bindings/phy/phy.h> 148 149 bus { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 153 torrent-phy@f0fb500000 { 154 compatible = "cdns,torrent-phy"; 155 reg = <0xf0 0xfb500000 0x0 0x00100000>, 156 <0xf0 0xfb030a00 0x0 0x00000040>; 157 reg-names = "torrent_phy", "dptx_phy"; 158 resets = <&phyrst 0>; 159 reset-names = "torrent_reset"; 160 clocks = <&ref_clk>; 161 clock-names = "refclk"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 phy@0 { 165 reg = <0>; 166 resets = <&phyrst 1>, <&phyrst 2>, 167 <&phyrst 3>, <&phyrst 4>; 168 #phy-cells = <0>; 169 cdns,phy-type = <PHY_TYPE_DP>; 170 cdns,num-lanes = <4>; 171 cdns,max-bit-rate = <8100>; 172 }; 173 }; 174 }; 175 - | 176 #include <dt-bindings/phy/phy.h> 177 #include <dt-bindings/phy/phy-cadence.h> 178 179 bus { 180 #address-cells = <2>; 181 #size-cells = <2>; 182 183 torrent-phy@f0fb500000 { 184 compatible = "cdns,torrent-phy"; 185 reg = <0xf0 0xfb500000 0x0 0x00100000>; 186 reg-names = "torrent_phy"; 187 resets = <&phyrst 0>, <&phyrst 1>; 188 reset-names = "torrent_reset", "torrent_apb"; 189 clocks = <&ref_clk>; 190 clock-names = "refclk"; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 phy@0 { 194 reg = <0>; 195 resets = <&phyrst 2>, <&phyrst 3>; 196 #phy-cells = <0>; 197 cdns,phy-type = <PHY_TYPE_PCIE>; 198 cdns,num-lanes = <2>; 199 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>; 200 }; 201 202 phy@2 { 203 reg = <2>; 204 resets = <&phyrst 4>; 205 #phy-cells = <0>; 206 cdns,phy-type = <PHY_TYPE_SGMII>; 207 cdns,num-lanes = <1>; 208 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>; 209 }; 210 }; 211 }; 212... 213