1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Cadence Torrent SD0801 PHY binding 8 9description: 10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) 11 hardware included with the Cadence MHDP DisplayPort controller. Torrent 12 PHY also supports multilink multiprotocol combinations including protocols 13 such as PCIe, USB, SGMII, QSGMII etc. 14 15maintainers: 16 - Swapnil Jakhade <sjakhade@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com> 18 19properties: 20 compatible: 21 enum: 22 - cdns,torrent-phy 23 - ti,j721e-serdes-10g 24 25 '#address-cells': 26 const: 1 27 28 '#size-cells': 29 const: 0 30 31 '#clock-cells': 32 const: 1 33 34 clocks: 35 minItems: 1 36 maxItems: 2 37 description: 38 PHY reference clock for 1 item. Must contain an entry in clock-names. 39 Optional Parent to enable output reference clock. 40 41 clock-names: 42 minItems: 1 43 items: 44 - const: refclk 45 - const: phy_en_refclk 46 47 assigned-clocks: 48 maxItems: 3 49 50 assigned-clock-parents: 51 maxItems: 3 52 53 reg: 54 minItems: 1 55 items: 56 - description: Offset of the Torrent PHY configuration registers. 57 - description: Offset of the DPTX PHY configuration registers. 58 59 reg-names: 60 minItems: 1 61 items: 62 - const: torrent_phy 63 - const: dptx_phy 64 65 resets: 66 minItems: 1 67 items: 68 - description: Torrent PHY reset. 69 - description: Torrent APB reset. This is optional. 70 71 reset-names: 72 minItems: 1 73 items: 74 - const: torrent_reset 75 - const: torrent_apb 76 77patternProperties: 78 '^phy@[0-3]$': 79 type: object 80 description: 81 Each group of PHY lanes with a single master lane should be represented as a sub-node. 82 properties: 83 reg: 84 description: 85 The master lane number. This is the lowest numbered lane in the lane group. 86 minimum: 0 87 maximum: 3 88 89 resets: 90 minItems: 1 91 maxItems: 4 92 description: 93 Contains list of resets, one per lane, to get all the link lanes out of reset. 94 95 "#phy-cells": 96 const: 0 97 98 cdns,phy-type: 99 description: 100 Specifies the type of PHY for which the group of PHY lanes is used. 101 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. 102 $ref: /schemas/types.yaml#/definitions/uint32 103 minimum: 1 104 maximum: 9 105 106 cdns,num-lanes: 107 description: 108 Number of lanes. 109 $ref: /schemas/types.yaml#/definitions/uint32 110 enum: [1, 2, 3, 4] 111 default: 4 112 113 cdns,ssc-mode: 114 description: 115 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, 116 EXTERNAL_SSC or INTERNAL_SSC. 117 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used. 118 $ref: /schemas/types.yaml#/definitions/uint32 119 enum: [0, 1, 2] 120 default: 0 121 122 cdns,max-bit-rate: 123 description: 124 Maximum DisplayPort link bit rate to use, in Mbps 125 $ref: /schemas/types.yaml#/definitions/uint32 126 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] 127 default: 8100 128 129 required: 130 - reg 131 - resets 132 - "#phy-cells" 133 - cdns,phy-type 134 - cdns,num-lanes 135 136 additionalProperties: false 137 138required: 139 - compatible 140 - "#address-cells" 141 - "#size-cells" 142 - clocks 143 - clock-names 144 - reg 145 - reg-names 146 - resets 147 - reset-names 148 149additionalProperties: false 150 151examples: 152 - | 153 #include <dt-bindings/phy/phy.h> 154 155 bus { 156 #address-cells = <2>; 157 #size-cells = <2>; 158 159 torrent-phy@f0fb500000 { 160 compatible = "cdns,torrent-phy"; 161 reg = <0xf0 0xfb500000 0x0 0x00100000>, 162 <0xf0 0xfb030a00 0x0 0x00000040>; 163 reg-names = "torrent_phy", "dptx_phy"; 164 resets = <&phyrst 0>; 165 reset-names = "torrent_reset"; 166 clocks = <&ref_clk>; 167 clock-names = "refclk"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 phy@0 { 171 reg = <0>; 172 resets = <&phyrst 1>, <&phyrst 2>, 173 <&phyrst 3>, <&phyrst 4>; 174 #phy-cells = <0>; 175 cdns,phy-type = <PHY_TYPE_DP>; 176 cdns,num-lanes = <4>; 177 cdns,max-bit-rate = <8100>; 178 }; 179 }; 180 }; 181 - | 182 #include <dt-bindings/phy/phy.h> 183 #include <dt-bindings/phy/phy-cadence.h> 184 185 bus { 186 #address-cells = <2>; 187 #size-cells = <2>; 188 189 torrent-phy@f0fb500000 { 190 compatible = "cdns,torrent-phy"; 191 reg = <0xf0 0xfb500000 0x0 0x00100000>; 192 reg-names = "torrent_phy"; 193 resets = <&phyrst 0>, <&phyrst 1>; 194 reset-names = "torrent_reset", "torrent_apb"; 195 clocks = <&ref_clk>; 196 clock-names = "refclk"; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 phy@0 { 200 reg = <0>; 201 resets = <&phyrst 2>, <&phyrst 3>; 202 #phy-cells = <0>; 203 cdns,phy-type = <PHY_TYPE_PCIE>; 204 cdns,num-lanes = <2>; 205 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>; 206 }; 207 208 phy@2 { 209 reg = <2>; 210 resets = <&phyrst 4>; 211 #phy-cells = <0>; 212 cdns,phy-type = <PHY_TYPE_SGMII>; 213 cdns,num-lanes = <1>; 214 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>; 215 }; 216 }; 217 }; 218... 219