xref: /freebsd/sys/contrib/device-tree/Bindings/phy/phy-cadence-sierra.yaml (revision 2eb4d8dc723da3cf7d735a3226ae49da4c8c5dbc) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Cadence Sierra PHY binding
8
9description:
10  This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
11  multiprotocol combinations including protocols such as PCIe, USB etc.
12
13maintainers:
14  - Swapnil Jakhade <sjakhade@cadence.com>
15  - Yuti Amonkar <yamonkar@cadence.com>
16
17properties:
18  compatible:
19    enum:
20      - cdns,sierra-phy-t0
21      - ti,sierra-phy-t0
22
23  '#address-cells':
24    const: 1
25
26  '#size-cells':
27    const: 0
28
29  '#clock-cells':
30    const: 1
31
32  resets:
33    minItems: 1
34    maxItems: 2
35    items:
36      - description: Sierra PHY reset.
37      - description: Sierra APB reset. This is optional.
38
39  reset-names:
40    minItems: 1
41    maxItems: 2
42    items:
43      - const: sierra_reset
44      - const: sierra_apb
45
46  reg:
47    maxItems: 1
48    description:
49      Offset of the Sierra PHY configuration registers.
50
51  reg-names:
52    const: serdes
53
54  clocks:
55    minItems: 2
56    maxItems: 4
57
58  clock-names:
59    minItems: 2
60    items:
61      - const: cmn_refclk_dig_div
62      - const: cmn_refclk1_dig_div
63      - const: pll0_refclk
64      - const: pll1_refclk
65
66  assigned-clocks:
67    minItems: 1
68    maxItems: 2
69
70  assigned-clock-parents:
71    minItems: 1
72    maxItems: 2
73
74  cdns,autoconf:
75    type: boolean
76    description:
77      A boolean property whose presence indicates that the PHY registers will be
78      configured by hardware. If not present, all sub-node optional properties
79      must be provided.
80
81patternProperties:
82  '^phy@[0-9a-f]$':
83    type: object
84    description:
85      Each group of PHY lanes with a single master lane should be represented as
86      a sub-node. Note that the actual configuration of each lane is determined
87      by hardware strapping, and must match the configuration specified here.
88    properties:
89      reg:
90        description:
91          The master lane number. This is the lowest numbered lane in the lane group.
92        minimum: 0
93        maximum: 15
94
95      resets:
96        minItems: 1
97        maxItems: 4
98        description:
99          Contains list of resets, one per lane, to get all the link lanes out of reset.
100
101      "#phy-cells":
102        const: 0
103
104      cdns,phy-type:
105        description:
106          Specifies the type of PHY for which the group of PHY lanes is used.
107          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
108        $ref: /schemas/types.yaml#/definitions/uint32
109        enum: [2, 4]
110
111      cdns,num-lanes:
112        description:
113          Number of lanes in this group. The group is made up of consecutive lanes.
114        $ref: /schemas/types.yaml#/definitions/uint32
115        minimum: 1
116        maximum: 16
117
118    required:
119      - reg
120      - resets
121      - "#phy-cells"
122
123    additionalProperties: false
124
125required:
126  - compatible
127  - "#address-cells"
128  - "#size-cells"
129  - reg
130  - resets
131  - reset-names
132
133additionalProperties: false
134
135examples:
136  - |
137    #include <dt-bindings/phy/phy.h>
138
139    bus {
140        #address-cells = <2>;
141        #size-cells = <2>;
142
143        sierra-phy@fd240000 {
144            compatible = "cdns,sierra-phy-t0";
145            reg = <0x0 0xfd240000 0x0 0x40000>;
146            resets = <&phyrst 0>, <&phyrst 1>;
147            reset-names = "sierra_reset", "sierra_apb";
148            clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
149            clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
150            #address-cells = <1>;
151            #size-cells = <0>;
152            pcie0_phy0: phy@0 {
153                reg = <0>;
154                resets = <&phyrst 2>;
155                cdns,num-lanes = <2>;
156                #phy-cells = <0>;
157                cdns,phy-type = <PHY_TYPE_PCIE>;
158            };
159            pcie0_phy1: phy@2 {
160                reg = <2>;
161                resets = <&phyrst 4>;
162                cdns,num-lanes = <1>;
163                #phy-cells = <0>;
164                cdns,phy-type = <PHY_TYPE_PCIE>;
165            };
166        };
167    };
168