xref: /freebsd/sys/contrib/device-tree/Bindings/phy/mixel,mipi-dsi-phy.yaml (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mixel DSI PHY for i.MX8
8
9maintainers:
10  - Guido Günther <agx@sigxcpu.org>
11
12description: |
13  The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
15  electrical signals for DSI.
16
17  The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
18  in either MIPI-DSI PHY mode or LVDS PHY mode.
19
20properties:
21  compatible:
22    enum:
23      - fsl,imx8mq-mipi-dphy
24      - fsl,imx8qxp-mipi-dphy
25
26  reg:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  clock-names:
33    const: phy_ref
34
35  "#phy-cells":
36    const: 0
37
38  fsl,syscon:
39    $ref: /schemas/types.yaml#/definitions/phandle
40    description: |
41      A phandle which points to Control and Status Registers(CSR) module.
42
43  power-domains:
44    maxItems: 1
45
46required:
47  - compatible
48  - reg
49  - clocks
50  - clock-names
51  - "#phy-cells"
52  - power-domains
53
54allOf:
55  - if:
56      properties:
57        compatible:
58          contains:
59            const: fsl,imx8mq-mipi-dphy
60    then:
61      properties:
62        fsl,syscon: false
63
64      required:
65        - assigned-clocks
66        - assigned-clock-parents
67        - assigned-clock-rates
68
69  - if:
70      properties:
71        compatible:
72          contains:
73            const: fsl,imx8qxp-mipi-dphy
74    then:
75      properties:
76        assigned-clocks: false
77        assigned-clock-parents: false
78        assigned-clock-rates: false
79
80      required:
81        - fsl,syscon
82
83additionalProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/clock/imx8mq-clock.h>
88    dphy: dphy@30a0030 {
89        compatible = "fsl,imx8mq-mipi-dphy";
90        reg = <0x30a00300 0x100>;
91        clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
92        clock-names = "phy_ref";
93        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
94        assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
95        assigned-clock-rates = <24000000>;
96        #phy-cells = <0>;
97        power-domains = <&pgc_mipi>;
98    };
99