xref: /freebsd/sys/contrib/device-tree/Bindings/phy/mixel,mipi-dsi-phy.yaml (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mixel DSI PHY for i.MX8

maintainers:
  - Guido Günther <agx@sigxcpu.org>

description: |
  The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
  electrical signals for DSI.

  The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
  in either MIPI-DSI PHY mode or LVDS PHY mode.

properties:
  compatible:
    enum:
      - fsl,imx8mq-mipi-dphy
      - fsl,imx8qxp-mipi-dphy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: phy_ref

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

  assigned-clock-rates:
    maxItems: 1

  "#phy-cells":
    const: 0

  fsl,syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      A phandle which points to Control and Status Registers(CSR) module.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#phy-cells"
  - power-domains

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mq-mipi-dphy
    then:
      properties:
        fsl,syscon: false

      required:
        - assigned-clocks
        - assigned-clock-parents
        - assigned-clock-rates

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8qxp-mipi-dphy
    then:
      properties:
        assigned-clocks: false
        assigned-clock-parents: false
        assigned-clock-rates: false

      required:
        - fsl,syscon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    dphy: dphy@30a0030 {
        compatible = "fsl,imx8mq-mipi-dphy";
        reg = <0x30a00300 0x100>;
        clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
        clock-names = "phy_ref";
        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
        assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
        assigned-clock-rates = <24000000>;
        #phy-cells = <0>;
        power-domains = <&pgc_mipi>;
    };