xref: /freebsd/sys/contrib/device-tree/Bindings/phy/mediatek,hdmi-phy.yaml (revision a90b9d0159070121c221b966469c3e36d912bf82) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek High Definition Multimedia Interface (HDMI) PHY
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: |
16  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17  output and drives the HDMI pads.
18
19properties:
20  $nodename:
21    pattern: "^hdmi-phy@[0-9a-f]+$"
22
23  compatible:
24    oneOf:
25      - items:
26          - enum:
27              - mediatek,mt7623-hdmi-phy
28          - const: mediatek,mt2701-hdmi-phy
29      - const: mediatek,mt2701-hdmi-phy
30      - const: mediatek,mt8173-hdmi-phy
31      - const: mediatek,mt8195-hdmi-phy
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    items:
38      - description: PLL reference clock
39
40  clock-names:
41    items:
42      - const: pll_ref
43
44  clock-output-names:
45    items:
46      - const: hdmitx_dig_cts
47
48  "#phy-cells":
49    const: 0
50
51  "#clock-cells":
52    const: 0
53
54  mediatek,ibias:
55    description:
56      TX DRV bias current for < 1.65Gbps
57    $ref: /schemas/types.yaml#/definitions/uint32
58    minimum: 0
59    maximum: 63
60    default: 0xa
61
62  mediatek,ibias_up:
63    description:
64      TX DRV bias current for >= 1.65Gbps
65    $ref: /schemas/types.yaml#/definitions/uint32
66    minimum: 0
67    maximum: 63
68    default: 0x1c
69
70required:
71  - compatible
72  - reg
73  - clocks
74  - clock-names
75  - clock-output-names
76  - "#phy-cells"
77  - "#clock-cells"
78
79additionalProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/clock/mt8173-clk.h>
84    hdmi_phy: hdmi-phy@10209100 {
85        compatible = "mediatek,mt8173-hdmi-phy";
86        reg = <0x10209100 0x24>;
87        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
88        clock-names = "pll_ref";
89        clock-output-names = "hdmitx_dig_cts";
90        mediatek,ibias = <0xa>;
91        mediatek,ibias_up = <0x1c>;
92        #clock-cells = <0>;
93        #phy-cells = <0>;
94    };
95
96...
97