1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek MIPI Display Serial Interface (DSI) PHY 9 10maintainers: 11 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 12 - Philipp Zabel <p.zabel@pengutronix.de> 13 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 15description: The MIPI DSI PHY supports up to 4-lane output. 16 17properties: 18 $nodename: 19 pattern: "^dsi-phy@[0-9a-f]+$" 20 21 compatible: 22 oneOf: 23 - items: 24 - enum: 25 - mediatek,mt7623-mipi-tx 26 - const: mediatek,mt2701-mipi-tx 27 - items: 28 - enum: 29 - mediatek,mt8365-mipi-tx 30 - const: mediatek,mt8183-mipi-tx 31 - const: mediatek,mt2701-mipi-tx 32 - const: mediatek,mt8173-mipi-tx 33 - const: mediatek,mt8183-mipi-tx 34 35 reg: 36 maxItems: 1 37 38 clocks: 39 items: 40 - description: PLL reference clock 41 42 clock-output-names: 43 maxItems: 1 44 45 "#phy-cells": 46 const: 0 47 48 "#clock-cells": 49 const: 0 50 51 nvmem-cells: 52 maxItems: 1 53 description: A phandle to the calibration data provided by a nvmem device, 54 if unspecified, default values shall be used. 55 56 nvmem-cell-names: 57 items: 58 - const: calibration-data 59 60 drive-strength-microamp: 61 description: adjust driving current 62 multipleOf: 200 63 minimum: 2000 64 maximum: 6000 65 default: 4600 66 67required: 68 - compatible 69 - reg 70 - clocks 71 - clock-output-names 72 - "#phy-cells" 73 - "#clock-cells" 74 75additionalProperties: false 76 77examples: 78 - | 79 #include <dt-bindings/clock/mt8173-clk.h> 80 dsi-phy@10215000 { 81 compatible = "mediatek,mt8173-mipi-tx"; 82 reg = <0x10215000 0x1000>; 83 clocks = <&clk26m>; 84 clock-output-names = "mipi_tx0_pll"; 85 drive-strength-microamp = <4000>; 86 nvmem-cells= <&mipi_tx_calibration>; 87 nvmem-cell-names = "calibration-data"; 88 #clock-cells = <0>; 89 #phy-cells = <0>; 90 }; 91 92... 93