1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek MIPI Display Serial Interface (DSI) PHY binding 9 10maintainers: 11 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 12 - Philipp Zabel <p.zabel@pengutronix.de> 13 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 15description: The MIPI DSI PHY supports up to 4-lane output. 16 17properties: 18 $nodename: 19 pattern: "^dsi-phy@[0-9a-f]+$" 20 21 compatible: 22 oneOf: 23 - items: 24 - enum: 25 - mediatek,mt7623-mipi-tx 26 - const: mediatek,mt2701-mipi-tx 27 - const: mediatek,mt2701-mipi-tx 28 - const: mediatek,mt8173-mipi-tx 29 - const: mediatek,mt8183-mipi-tx 30 31 reg: 32 maxItems: 1 33 34 clocks: 35 items: 36 - description: PLL reference clock 37 38 clock-output-names: 39 maxItems: 1 40 41 "#phy-cells": 42 const: 0 43 44 "#clock-cells": 45 const: 0 46 47 nvmem-cells: 48 maxItems: 1 49 description: A phandle to the calibration data provided by a nvmem device, 50 if unspecified, default values shall be used. 51 52 nvmem-cell-names: 53 items: 54 - const: calibration-data 55 56 drive-strength-microamp: 57 description: adjust driving current 58 multipleOf: 200 59 minimum: 2000 60 maximum: 6000 61 default: 4600 62 63required: 64 - compatible 65 - reg 66 - clocks 67 - clock-output-names 68 - "#phy-cells" 69 - "#clock-cells" 70 71additionalProperties: false 72 73examples: 74 - | 75 #include <dt-bindings/clock/mt8173-clk.h> 76 dsi-phy@10215000 { 77 compatible = "mediatek,mt8173-mipi-tx"; 78 reg = <0x10215000 0x1000>; 79 clocks = <&clk26m>; 80 clock-output-names = "mipi_tx0_pll"; 81 drive-strength-microamp = <4000>; 82 nvmem-cells= <&mipi_tx_calibration>; 83 nvmem-cell-names = "calibration-data"; 84 #clock-cells = <0>; 85 #phy-cells = <0>; 86 }; 87 88... 89