1*01950c46SEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*01950c46SEmmanuel Vadot%YAML 1.2 3*01950c46SEmmanuel Vadot--- 4*01950c46SEmmanuel Vadot$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# 5*01950c46SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*01950c46SEmmanuel Vadot 7*01950c46SEmmanuel Vadottitle: Arm Coresight Performance Monitoring Unit Architecture 8*01950c46SEmmanuel Vadot 9*01950c46SEmmanuel Vadotmaintainers: 10*01950c46SEmmanuel Vadot - Robin Murphy <robin.murphy@arm.com> 11*01950c46SEmmanuel Vadot 12*01950c46SEmmanuel Vadotproperties: 13*01950c46SEmmanuel Vadot compatible: 14*01950c46SEmmanuel Vadot const: arm,coresight-pmu 15*01950c46SEmmanuel Vadot 16*01950c46SEmmanuel Vadot reg: 17*01950c46SEmmanuel Vadot items: 18*01950c46SEmmanuel Vadot - description: Register page 0 19*01950c46SEmmanuel Vadot - description: Register page 1, if the PMU implements the dual-page extension 20*01950c46SEmmanuel Vadot minItems: 1 21*01950c46SEmmanuel Vadot 22*01950c46SEmmanuel Vadot interrupts: 23*01950c46SEmmanuel Vadot items: 24*01950c46SEmmanuel Vadot - description: Overflow interrupt 25*01950c46SEmmanuel Vadot 26*01950c46SEmmanuel Vadot cpus: 27*01950c46SEmmanuel Vadot description: If the PMU is associated with a particular CPU or subset of CPUs, 28*01950c46SEmmanuel Vadot array of phandles to the appropriate CPU node(s) 29*01950c46SEmmanuel Vadot 30*01950c46SEmmanuel Vadot reg-io-width: 31*01950c46SEmmanuel Vadot description: Granularity at which PMU register accesses are single-copy atomic 32*01950c46SEmmanuel Vadot default: 4 33*01950c46SEmmanuel Vadot enum: [4, 8] 34*01950c46SEmmanuel Vadot 35*01950c46SEmmanuel Vadotrequired: 36*01950c46SEmmanuel Vadot - compatible 37*01950c46SEmmanuel Vadot - reg 38*01950c46SEmmanuel Vadot 39*01950c46SEmmanuel VadotadditionalProperties: false 40