1Socionext UniPhier PCIe host controller bindings 2 3This describes the devicetree bindings for PCIe host controller implemented 4on Socionext UniPhier SoCs. 5 6UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. 7It shares common functions with the PCIe DesignWare core driver and inherits 8common properties defined in 9Documentation/devicetree/bindings/pci/designware-pcie.txt. 10 11Required properties: 12- compatible: Should be "socionext,uniphier-pcie". 13- reg: Specifies offset and length of the register set for the device. 14 According to the reg-names, appropriate register sets are required. 15- reg-names: Must include the following entries: 16 "dbi" - controller configuration registers 17 "link" - SoC-specific glue layer registers 18 "config" - PCIe configuration space 19- clocks: A phandle to the clock gate for PCIe glue layer including 20 the host controller. 21- resets: A phandle to the reset line for PCIe glue layer including 22 the host controller. 23- interrupts: A list of interrupt specifiers. According to the 24 interrupt-names, appropriate interrupts are required. 25- interrupt-names: Must include the following entries: 26 "dma" - DMA interrupt 27 "msi" - MSI interrupt 28 29Optional properties: 30- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate 31 phys are required. 32- phy-names: Must be "pcie-phy". 33 34Required sub-node: 35- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI 36 interrupts. 37 38Required properties for legacy-interrupt-controller: 39- interrupt-controller: identifies the node as an interrupt controller. 40- #interrupt-cells: specifies the number of cells needed to encode an 41 interrupt source. The value must be 1. 42- interrupt-parent: Phandle to the parent interrupt controller. 43- interrupts: An interrupt specifier for legacy interrupt. 44 45Example: 46 47 pcie: pcie@66000000 { 48 compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 49 status = "disabled"; 50 reg-names = "dbi", "link", "config"; 51 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 52 <0x2fff0000 0x10000>; 53 #address-cells = <3>; 54 #size-cells = <2>; 55 clocks = <&sys_clk 24>; 56 resets = <&sys_rst 24>; 57 num-lanes = <1>; 58 num-viewport = <1>; 59 bus-range = <0x0 0xff>; 60 device_type = "pci"; 61 ranges = 62 /* downstream I/O */ 63 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000 64 /* non-prefetchable memory */ 65 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>; 66 #interrupt-cells = <1>; 67 interrupt-names = "dma", "msi"; 68 interrupts = <0 224 4>, <0 225 4>; 69 interrupt-map-mask = <0 0 0 7>; 70 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 71 <0 0 0 2 &pcie_intc 1>, /* INTB */ 72 <0 0 0 3 &pcie_intc 2>, /* INTC */ 73 <0 0 0 4 &pcie_intc 3>; /* INTD */ 74 75 pcie_intc: legacy-interrupt-controller { 76 interrupt-controller; 77 #interrupt-cells = <1>; 78 interrupt-parent = <&gic>; 79 interrupts = <0 226 4>; 80 }; 81 }; 82