xref: /freebsd/sys/contrib/device-tree/Bindings/pci/ti,j721e-pci-host.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI J721E PCI Host (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13properties:
14  compatible:
15    oneOf:
16      - const: ti,j721e-pcie-host
17      - const: ti,j784s4-pcie-host
18      - description: PCIe controller in AM64
19        items:
20          - const: ti,am64-pcie-host
21          - const: ti,j721e-pcie-host
22      - description: PCIe controller in J7200
23        items:
24          - const: ti,j7200-pcie-host
25          - const: ti,j721e-pcie-host
26
27  reg:
28    maxItems: 4
29
30  reg-names:
31    items:
32      - const: intd_cfg
33      - const: user_cfg
34      - const: reg
35      - const: cfg
36
37  ti,syscon-pcie-ctrl:
38    $ref: /schemas/types.yaml#/definitions/phandle-array
39    items:
40      - items:
41          - description: Phandle to the SYSCON entry
42          - description: pcie_ctrl register offset within SYSCON
43    description: Specifier for configuring PCIe mode and link speed.
44
45  power-domains:
46    maxItems: 1
47
48  clocks:
49    minItems: 1
50    maxItems: 2
51    description: |+
52      clock-specifier to represent input to the PCIe for 1 item.
53      2nd item if present represents reference clock to the connector.
54
55  clock-names:
56    minItems: 1
57    items:
58      - const: fck
59      - const: pcie_refclk
60
61  dma-coherent: true
62
63  vendor-id:
64    const: 0x104c
65
66  device-id:
67    enum:
68      - 0xb00d
69      - 0xb00f
70      - 0xb010
71      - 0xb013
72
73  msi-map: true
74
75  interrupts:
76    maxItems: 1
77
78  interrupt-names:
79    items:
80      - const: link_state
81
82  interrupt-controller:
83    type: object
84    additionalProperties: false
85
86    properties:
87      interrupt-controller: true
88
89      '#interrupt-cells':
90        const: 1
91
92      interrupts:
93        maxItems: 1
94
95allOf:
96  - $ref: cdns-pcie-host.yaml#
97  - if:
98      properties:
99        compatible:
100          enum:
101            - ti,am64-pcie-host
102    then:
103      properties:
104        num-lanes:
105          const: 1
106
107  - if:
108      properties:
109        compatible:
110          enum:
111            - ti,j7200-pcie-host
112            - ti,j721e-pcie-host
113    then:
114      properties:
115        num-lanes:
116          minimum: 1
117          maximum: 2
118
119  - if:
120      properties:
121        compatible:
122          enum:
123            - ti,j784s4-pcie-host
124    then:
125      properties:
126        num-lanes:
127          minimum: 1
128          maximum: 4
129
130required:
131  - compatible
132  - reg
133  - reg-names
134  - ti,syscon-pcie-ctrl
135  - max-link-speed
136  - num-lanes
137  - power-domains
138  - clocks
139  - clock-names
140  - vendor-id
141  - device-id
142  - msi-map
143  - dma-ranges
144  - ranges
145  - reset-gpios
146  - phys
147  - phy-names
148
149unevaluatedProperties: false
150
151examples:
152  - |
153    #include <dt-bindings/soc/ti,sci_pm_domain.h>
154    #include <dt-bindings/gpio/gpio.h>
155
156    bus {
157        #address-cells = <2>;
158        #size-cells = <2>;
159
160        pcie0_rc: pcie@2900000 {
161            compatible = "ti,j721e-pcie-host";
162            reg = <0x00 0x02900000 0x00 0x1000>,
163                  <0x00 0x02907000 0x00 0x400>,
164                  <0x00 0x0d000000 0x00 0x00800000>,
165                  <0x00 0x10000000 0x00 0x00001000>;
166            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
167            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
168            max-link-speed = <3>;
169            num-lanes = <2>;
170            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
171            clocks = <&k3_clks 239 1>;
172            clock-names = "fck";
173            device_type = "pci";
174            #address-cells = <3>;
175            #size-cells = <2>;
176            bus-range = <0x0 0xf>;
177            vendor-id = <0x104c>;
178            device-id = <0xb00d>;
179            msi-map = <0x0 &gic_its 0x0 0x10000>;
180            dma-coherent;
181            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
182            phys = <&serdes0_pcie_link>;
183            phy-names = "pcie-phy";
184            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
185                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
186            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
187        };
188    };
189