xref: /freebsd/sys/contrib/device-tree/Bindings/pci/ti,j721e-pci-host.yaml (revision 2e3507c25e42292b45a5482e116d278f5515d04d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI J721E PCI Host (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13allOf:
14  - $ref: cdns-pcie-host.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: ti,j721e-pcie-host
20      - description: PCIe controller in AM64
21        items:
22          - const: ti,am64-pcie-host
23          - const: ti,j721e-pcie-host
24      - description: PCIe controller in J7200
25        items:
26          - const: ti,j7200-pcie-host
27          - const: ti,j721e-pcie-host
28
29  reg:
30    maxItems: 4
31
32  reg-names:
33    items:
34      - const: intd_cfg
35      - const: user_cfg
36      - const: reg
37      - const: cfg
38
39  ti,syscon-pcie-ctrl:
40    $ref: /schemas/types.yaml#/definitions/phandle-array
41    items:
42      - items:
43          - description: Phandle to the SYSCON entry
44          - description: pcie_ctrl register offset within SYSCON
45    description: Specifier for configuring PCIe mode and link speed.
46
47  power-domains:
48    maxItems: 1
49
50  clocks:
51    minItems: 1
52    maxItems: 2
53    description: |+
54      clock-specifier to represent input to the PCIe for 1 item.
55      2nd item if present represents reference clock to the connector.
56
57  clock-names:
58    minItems: 1
59    items:
60      - const: fck
61      - const: pcie_refclk
62
63  dma-coherent: true
64
65  vendor-id:
66    const: 0x104c
67
68  device-id:
69    enum:
70      - 0xb00d
71      - 0xb00f
72      - 0xb010
73      - 0xb013
74
75  msi-map: true
76
77  interrupts:
78    maxItems: 1
79
80  interrupt-names:
81    items:
82      - const: link_state
83
84  interrupt-controller:
85    type: object
86    additionalProperties: false
87
88    properties:
89      interrupt-controller: true
90
91      '#interrupt-cells':
92        const: 1
93
94      interrupts:
95        maxItems: 1
96
97required:
98  - compatible
99  - reg
100  - reg-names
101  - ti,syscon-pcie-ctrl
102  - max-link-speed
103  - num-lanes
104  - power-domains
105  - clocks
106  - clock-names
107  - vendor-id
108  - device-id
109  - msi-map
110  - dma-ranges
111  - ranges
112  - reset-gpios
113  - phys
114  - phy-names
115
116unevaluatedProperties: false
117
118examples:
119  - |
120    #include <dt-bindings/soc/ti,sci_pm_domain.h>
121    #include <dt-bindings/gpio/gpio.h>
122
123    bus {
124        #address-cells = <2>;
125        #size-cells = <2>;
126
127        pcie0_rc: pcie@2900000 {
128            compatible = "ti,j721e-pcie-host";
129            reg = <0x00 0x02900000 0x00 0x1000>,
130                  <0x00 0x02907000 0x00 0x400>,
131                  <0x00 0x0d000000 0x00 0x00800000>,
132                  <0x00 0x10000000 0x00 0x00001000>;
133            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
134            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
135            max-link-speed = <3>;
136            num-lanes = <2>;
137            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
138            clocks = <&k3_clks 239 1>;
139            clock-names = "fck";
140            device_type = "pci";
141            #address-cells = <3>;
142            #size-cells = <2>;
143            bus-range = <0x0 0xf>;
144            vendor-id = <0x104c>;
145            device-id = <0xb00d>;
146            msi-map = <0x0 &gic_its 0x0 0x10000>;
147            dma-coherent;
148            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
149            phys = <&serdes0_pcie_link>;
150            phy-names = "pcie-phy";
151            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
152                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
153            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
154        };
155    };
156