xref: /freebsd/sys/contrib/device-tree/Bindings/pci/sifive,fu740-pcie.yaml (revision 3c4ba5f55438f7afd4f4b0b56f88f2bb505fd6a6) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive FU740 PCIe host controller
8
9description: |+
10  SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
11  PCI core. It shares common features with the PCIe DesignWare core and
12  inherits common properties defined in
13  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
14
15maintainers:
16  - Paul Walmsley <paul.walmsley@sifive.com>
17  - Greentime Hu <greentime.hu@sifive.com>
18
19allOf:
20  - $ref: /schemas/pci/snps,dw-pcie.yaml#
21
22properties:
23  compatible:
24    const: sifive,fu740-pcie
25
26  reg:
27    maxItems: 3
28
29  reg-names:
30    items:
31      - const: dbi
32      - const: config
33      - const: mgmt
34
35  dma-coherent: true
36
37  num-lanes:
38    const: 8
39
40  msi-parent: true
41
42  interrupt-names:
43    items:
44      - const: msi
45      - const: inta
46      - const: intb
47      - const: intc
48      - const: intd
49
50  resets:
51    description: A phandle to the PCIe power up reset line.
52    maxItems: 1
53
54  pwren-gpios:
55    description: Should specify the GPIO for controlling the PCI bus device power on.
56    maxItems: 1
57
58  reset-gpios:
59    maxItems: 1
60
61required:
62  - dma-coherent
63  - num-lanes
64  - interrupts
65  - interrupt-names
66  - interrupt-map-mask
67  - interrupt-map
68  - clocks
69  - resets
70  - pwren-gpios
71  - reset-gpios
72
73unevaluatedProperties: false
74
75examples:
76  - |
77    bus {
78        #address-cells = <2>;
79        #size-cells = <2>;
80        #include <dt-bindings/clock/sifive-fu740-prci.h>
81
82        pcie@e00000000 {
83            compatible = "sifive,fu740-pcie";
84            #address-cells = <3>;
85            #size-cells = <2>;
86            #interrupt-cells = <1>;
87            reg = <0xe 0x00000000 0x0 0x80000000>,
88                  <0xd 0xf0000000 0x0 0x10000000>,
89                  <0x0 0x100d0000 0x0 0x1000>;
90            reg-names = "dbi", "config", "mgmt";
91            device_type = "pci";
92            dma-coherent;
93            bus-range = <0x0 0xff>;
94            ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
95                     <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
96                     <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
97                     <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
98            num-lanes = <0x8>;
99            interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
100            interrupt-names = "msi", "inta", "intb", "intc", "intd";
101            interrupt-parent = <&plic0>;
102            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
103            interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
104                            <0x0 0x0 0x0 0x2 &plic0 58>,
105                            <0x0 0x0 0x0 0x3 &plic0 59>,
106                            <0x0 0x0 0x0 0x4 &plic0 60>;
107            clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
108            resets = <&prci 4>;
109            pwren-gpios = <&gpio 5 0>;
110            reset-gpios = <&gpio 8 0>;
111        };
112    };
113