1* Rockchip AXI PCIe Endpoint Controller DT description 2 3Required properties: 4- compatible: Should contain "rockchip,rk3399-pcie-ep" 5- reg: Two register ranges as listed in the reg-names property 6- reg-names: Must include the following names 7 - "apb-base" 8 - "mem-base" 9- clocks: Must contain an entry for each entry in clock-names. 10 See ../clocks/clock-bindings.txt for details. 11- clock-names: Must include the following entries: 12 - "aclk" 13 - "aclk-perf" 14 - "hclk" 15 - "pm" 16- resets: Must contain seven entries for each entry in reset-names. 17 See ../reset/reset.txt for details. 18- reset-names: Must include the following names 19 - "core" 20 - "mgmt" 21 - "mgmt-sticky" 22 - "pipe" 23 - "pm" 24 - "aclk" 25 - "pclk" 26- pinctrl-names : The pin control state names 27- pinctrl-0: The "default" pinctrl state 28- phys: Must contain an phandle to a PHY for each entry in phy-names. 29- phy-names: Must include 4 entries for all 4 lanes even if some of 30 them won't be used for your cases. Entries are of the form "pcie-phy-N": 31 where N ranges from 0 to 3. 32 (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt 33 for changing the #phy-cells of phy node to support it) 34- rockchip,max-outbound-regions: Maximum number of outbound regions 35 36Optional Property: 37- num-lanes: number of lanes to use 38- max-functions: Maximum number of functions that can be configured (default 1). 39 40pcie0-ep: pcie@f8000000 { 41 compatible = "rockchip,rk3399-pcie-ep"; 42 #address-cells = <3>; 43 #size-cells = <2>; 44 rockchip,max-outbound-regions = <16>; 45 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 46 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 47 clock-names = "aclk", "aclk-perf", 48 "hclk", "pm"; 49 max-functions = /bits/ 8 <8>; 50 num-lanes = <4>; 51 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; 52 reg-names = "apb-base", "mem-base"; 53 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 54 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 55 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; 56 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 57 "pm", "pclk", "aclk"; 58 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; 59 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pcie_clkreq>; 62}; 63