xref: /freebsd/sys/contrib/device-tree/Bindings/pci/rockchip-dw-pcie.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
8
9maintainers:
10  - Shawn Lin <shawn.lin@rock-chips.com>
11  - Simon Xue <xxm@rock-chips.com>
12  - Heiko Stuebner <heiko@sntech.de>
13
14description: |+
15  RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
16  PCIe IP and thus inherits all the common properties defined in
17  snps,dw-pcie.yaml.
18
19properties:
20  compatible:
21    oneOf:
22      - const: rockchip,rk3568-pcie
23      - items:
24          - enum:
25              - rockchip,rk3562-pcie
26              - rockchip,rk3576-pcie
27              - rockchip,rk3588-pcie
28          - const: rockchip,rk3568-pcie
29
30  reg:
31    items:
32      - description: Data Bus Interface (DBI) registers
33      - description: Rockchip designed configuration registers
34      - description: Config registers
35
36  reg-names:
37    items:
38      - const: dbi
39      - const: apb
40      - const: config
41
42  legacy-interrupt-controller:
43    description: Interrupt controller node for handling legacy PCI interrupts.
44    type: object
45    additionalProperties: false
46    properties:
47      "#address-cells":
48        const: 0
49
50      "#interrupt-cells":
51        const: 1
52
53      interrupt-controller: true
54
55      interrupts:
56        items:
57          - description: combined legacy interrupt
58    required:
59      - "#address-cells"
60      - "#interrupt-cells"
61      - interrupt-controller
62      - interrupts
63
64  msi-map: true
65
66  ranges:
67    minItems: 2
68    maxItems: 3
69
70  vpcie3v3-supply: true
71
72allOf:
73  - $ref: /schemas/pci/snps,dw-pcie.yaml#
74  - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
75  - if:
76      not:
77        properties:
78          compatible:
79            contains:
80              enum:
81                - rockchip,rk3562-pcie
82                - rockchip,rk3576-pcie
83    then:
84      required:
85        - msi-map
86
87  - if:
88      properties:
89        compatible:
90          contains:
91            enum:
92              - rockchip,rk3562-pcie
93              - rockchip,rk3576-pcie
94    then:
95      properties:
96        interrupts:
97          minItems: 6
98          maxItems: 6
99        interrupt-names:
100          items:
101            - const: sys
102            - const: pmc
103            - const: msg
104            - const: legacy
105            - const: err
106            - const: msi
107    else:
108      properties:
109        interrupts:
110          minItems: 5
111        interrupt-names:
112          minItems: 5
113          items:
114            - const: sys
115            - const: pmc
116            - const: msg
117            - const: legacy
118            - const: err
119            - const: dma0
120            - const: dma1
121            - const: dma2
122            - const: dma3
123
124
125unevaluatedProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130
131    bus {
132        #address-cells = <2>;
133        #size-cells = <2>;
134
135        pcie3x2: pcie@fe280000 {
136            compatible = "rockchip,rk3568-pcie";
137            reg = <0x3 0xc0800000 0x0 0x390000>,
138                  <0x0 0xfe280000 0x0 0x10000>,
139                  <0x3 0x80000000 0x0 0x100000>;
140            reg-names = "dbi", "apb", "config";
141            bus-range = <0x20 0x2f>;
142            clocks = <&cru 143>, <&cru 144>,
143                     <&cru 145>, <&cru 146>,
144                     <&cru 147>;
145            clock-names = "aclk_mst", "aclk_slv",
146                          "aclk_dbi", "pclk",
147                          "aux";
148            device_type = "pci";
149            interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
150                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
151                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
152                         <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
153                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
154            interrupt-names = "sys", "pmc", "msg", "legacy", "err";
155            linux,pci-domain = <2>;
156            max-link-speed = <2>;
157            msi-map = <0x2000 &its 0x2000 0x1000>;
158            num-lanes = <2>;
159            phys = <&pcie30phy>;
160            phy-names = "pcie-phy";
161            power-domains = <&power 15>;
162            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
163                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
164            resets = <&cru 193>;
165            reset-names = "pipe";
166            #address-cells = <3>;
167            #size-cells = <2>;
168
169            legacy-interrupt-controller {
170                interrupt-controller;
171                #address-cells = <0>;
172                #interrupt-cells = <1>;
173                interrupt-parent = <&gic>;
174                interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
175            };
176        };
177    };
178...
179