1* Renesas R-Car PCIe interface 2 3Required properties: 4compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; 5 "renesas,pcie-r8a7744" for the R8A7744 SoC; 6 "renesas,pcie-r8a774a1" for the R8A774A1 SoC; 7 "renesas,pcie-r8a774b1" for the R8A774B1 SoC; 8 "renesas,pcie-r8a774c0" for the R8A774C0 SoC; 9 "renesas,pcie-r8a7779" for the R8A7779 SoC; 10 "renesas,pcie-r8a7790" for the R8A7790 SoC; 11 "renesas,pcie-r8a7791" for the R8A7791 SoC; 12 "renesas,pcie-r8a7793" for the R8A7793 SoC; 13 "renesas,pcie-r8a7795" for the R8A7795 SoC; 14 "renesas,pcie-r8a7796" for the R8A77960 SoC; 15 "renesas,pcie-r8a77961" for the R8A77961 SoC; 16 "renesas,pcie-r8a77980" for the R8A77980 SoC; 17 "renesas,pcie-r8a77990" for the R8A77990 SoC; 18 "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or 19 RZ/G1 compatible device. 20 "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or 21 RZ/G2 compatible device. 22 23 When compatible with the generic version, nodes must list the 24 SoC-specific version corresponding to the platform first 25 followed by the generic version. 26 27- reg: base address and length of the PCIe controller registers. 28- #address-cells: set to <3> 29- #size-cells: set to <2> 30- bus-range: PCI bus numbers covered 31- device_type: set to "pci" 32- ranges: ranges for the PCI memory and I/O regions. 33- dma-ranges: ranges for the inbound memory regions. 34- interrupts: two interrupt sources for MSI interrupts, followed by interrupt 35 source for hardware related interrupts (e.g. link speed change). 36- #interrupt-cells: set to <1> 37- interrupt-map-mask and interrupt-map: standard PCI properties 38 to define the mapping of the PCIe interface to interrupt numbers. 39- clocks: from common clock binding: clock specifiers for the PCIe controller 40 and PCIe bus clocks. 41- clock-names: from common clock binding: should be "pcie" and "pcie_bus". 42 43Optional properties: 44- phys: from common PHY binding: PHY phandle and specifier (only make sense 45 for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). 46- phy-names: from common PHY binding: should be "pcie". 47 48Example: 49 50SoC-specific DT Entry: 51 52 pcie: pcie@fe000000 { 53 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; 54 reg = <0 0xfe000000 0 0x80000>; 55 #address-cells = <3>; 56 #size-cells = <2>; 57 bus-range = <0x00 0xff>; 58 device_type = "pci"; 59 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 60 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 61 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 62 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 63 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 64 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; 65 interrupts = <0 116 4>, <0 117 4>, <0 118 4>; 66 #interrupt-cells = <1>; 67 interrupt-map-mask = <0 0 0 0>; 68 interrupt-map = <0 0 0 0 &gic 0 116 4>; 69 clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; 70 clock-names = "pcie", "pcie_bus"; 71 }; 72