xref: /freebsd/sys/contrib/device-tree/Bindings/pci/rcar-pci-host.yaml (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Renesas Electronics Corp.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Renesas R-Car PCIe Host
9
10maintainers:
11  - Marek Vasut <marek.vasut+renesas@gmail.com>
12  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13
14allOf:
15  - $ref: pci-bus.yaml#
16
17properties:
18  compatible:
19    oneOf:
20      - const: renesas,pcie-r8a7779       # R-Car H1
21      - items:
22          - enum:
23              - renesas,pcie-r8a7742      # RZ/G1H
24              - renesas,pcie-r8a7743      # RZ/G1M
25              - renesas,pcie-r8a7744      # RZ/G1N
26              - renesas,pcie-r8a7790      # R-Car H2
27              - renesas,pcie-r8a7791      # R-Car M2-W
28              - renesas,pcie-r8a7793      # R-Car M2-N
29          - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
30      - items:
31          - enum:
32              - renesas,pcie-r8a774a1     # RZ/G2M
33              - renesas,pcie-r8a774b1     # RZ/G2N
34              - renesas,pcie-r8a774c0     # RZ/G2E
35              - renesas,pcie-r8a774e1     # RZ/G2H
36              - renesas,pcie-r8a7795      # R-Car H3
37              - renesas,pcie-r8a7796      # R-Car M3-W
38              - renesas,pcie-r8a77961     # R-Car M3-W+
39              - renesas,pcie-r8a77965     # R-Car M3-N
40              - renesas,pcie-r8a77980     # R-Car V3H
41              - renesas,pcie-r8a77990     # R-Car E3
42          - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
43
44  reg:
45    maxItems: 1
46
47  interrupts:
48    minItems: 3
49    maxItems: 3
50
51  clocks:
52    maxItems: 2
53
54  clock-names:
55    items:
56      - const: pcie
57      - const: pcie_bus
58
59  power-domains:
60    maxItems: 1
61
62  resets:
63    maxItems: 1
64
65  phys:
66    maxItems: 1
67
68  phy-names:
69    const: pcie
70
71required:
72  - compatible
73  - reg
74  - interrupts
75  - clocks
76  - clock-names
77  - power-domains
78
79if:
80  not:
81    properties:
82      compatible:
83        contains:
84          const: renesas,pcie-r8a7779
85then:
86  required:
87    - resets
88
89unevaluatedProperties: false
90
91examples:
92  - |
93    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
94    #include <dt-bindings/interrupt-controller/arm-gic.h>
95    #include <dt-bindings/power/r8a7791-sysc.h>
96
97    soc {
98        #address-cells = <2>;
99        #size-cells = <2>;
100
101        pcie: pcie@fe000000 {
102            compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
103            reg = <0 0xfe000000 0 0x80000>;
104             #address-cells = <3>;
105             #size-cells = <2>;
106             bus-range = <0x00 0xff>;
107             device_type = "pci";
108             ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
109                      <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
110                      <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
111                      <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
112             dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
113                          <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
114             interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
115                          <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
116                          <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
117             #interrupt-cells = <1>;
118             interrupt-map-mask = <0 0 0 0>;
119             interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
120             clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
121             clock-names = "pcie", "pcie_bus";
122             power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
123             resets = <&cpg 319>;
124         };
125    };
126