1* Qualcomm PCI express root complex 2 3- compatible: 4 Usage: required 5 Value type: <stringlist> 6 Definition: Value should contain 7 - "qcom,pcie-ipq8064" for ipq8064 8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 9 - "qcom,pcie-apq8064" for apq8064 10 - "qcom,pcie-apq8084" for apq8084 11 - "qcom,pcie-msm8996" for msm8996 or apq8096 12 - "qcom,pcie-ipq4019" for ipq4019 13 - "qcom,pcie-ipq8074" for ipq8074 14 - "qcom,pcie-qcs404" for qcs404 15 - "qcom,pcie-sc8180x" for sc8180x 16 - "qcom,pcie-sdm845" for sdm845 17 - "qcom,pcie-sm8250" for sm8250 18 - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 19 - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 20 - "qcom,pcie-ipq6018" for ipq6018 21 22- reg: 23 Usage: required 24 Value type: <prop-encoded-array> 25 Definition: Register ranges as listed in the reg-names property 26 27- reg-names: 28 Usage: required 29 Value type: <stringlist> 30 Definition: Must include the following entries 31 - "parf" Qualcomm specific registers 32 - "dbi" DesignWare PCIe registers 33 - "elbi" External local bus interface registers 34 - "config" PCIe configuration space 35 - "atu" ATU address space (optional) 36 37- device_type: 38 Usage: required 39 Value type: <string> 40 Definition: Should be "pci". As specified in snps,dw-pcie.yaml 41 42- #address-cells: 43 Usage: required 44 Value type: <u32> 45 Definition: Should be 3. As specified in snps,dw-pcie.yaml 46 47- #size-cells: 48 Usage: required 49 Value type: <u32> 50 Definition: Should be 2. As specified in snps,dw-pcie.yaml 51 52- ranges: 53 Usage: required 54 Value type: <prop-encoded-array> 55 Definition: As specified in snps,dw-pcie.yaml 56 57- interrupts: 58 Usage: required 59 Value type: <prop-encoded-array> 60 Definition: MSI interrupt 61 62- interrupt-names: 63 Usage: required 64 Value type: <stringlist> 65 Definition: Should contain "msi" 66 67- #interrupt-cells: 68 Usage: required 69 Value type: <u32> 70 Definition: Should be 1. As specified in snps,dw-pcie.yaml 71 72- interrupt-map-mask: 73 Usage: required 74 Value type: <prop-encoded-array> 75 Definition: As specified in snps,dw-pcie.yaml 76 77- interrupt-map: 78 Usage: required 79 Value type: <prop-encoded-array> 80 Definition: As specified in snps,dw-pcie.yaml 81 82- clocks: 83 Usage: required 84 Value type: <prop-encoded-array> 85 Definition: List of phandle and clock specifier pairs as listed 86 in clock-names property 87 88- clock-names: 89 Usage: required 90 Value type: <stringlist> 91 Definition: Should contain the following entries 92 - "iface" Configuration AHB clock 93 94- clock-names: 95 Usage: required for ipq/apq8064 96 Value type: <stringlist> 97 Definition: Should contain the following entries 98 - "core" Clocks the pcie hw block 99 - "phy" Clocks the pcie PHY block 100 - "aux" Clocks the pcie AUX block 101 - "ref" Clocks the pcie ref block 102- clock-names: 103 Usage: required for apq8084/ipq4019 104 Value type: <stringlist> 105 Definition: Should contain the following entries 106 - "aux" Auxiliary (AUX) clock 107 - "bus_master" Master AXI clock 108 - "bus_slave" Slave AXI clock 109 110- clock-names: 111 Usage: required for msm8996/apq8096 112 Value type: <stringlist> 113 Definition: Should contain the following entries 114 - "pipe" Pipe Clock driving internal logic 115 - "aux" Auxiliary (AUX) clock 116 - "cfg" Configuration clock 117 - "bus_master" Master AXI clock 118 - "bus_slave" Slave AXI clock 119 120- clock-names: 121 Usage: required for ipq8074 122 Value type: <stringlist> 123 Definition: Should contain the following entries 124 - "iface" PCIe to SysNOC BIU clock 125 - "axi_m" AXI Master clock 126 - "axi_s" AXI Slave clock 127 - "ahb" AHB clock 128 - "aux" Auxiliary clock 129 130- clock-names: 131 Usage: required for ipq6018 132 Value type: <stringlist> 133 Definition: Should contain the following entries 134 - "iface" PCIe to SysNOC BIU clock 135 - "axi_m" AXI Master clock 136 - "axi_s" AXI Slave clock 137 - "axi_bridge" AXI bridge clock 138 - "rchng" 139 140- clock-names: 141 Usage: required for qcs404 142 Value type: <stringlist> 143 Definition: Should contain the following entries 144 - "iface" AHB clock 145 - "aux" Auxiliary clock 146 - "master_bus" AXI Master clock 147 - "slave_bus" AXI Slave clock 148 149- clock-names: 150 Usage: required for sdm845 151 Value type: <stringlist> 152 Definition: Should contain the following entries 153 - "aux" Auxiliary clock 154 - "cfg" Configuration clock 155 - "bus_master" Master AXI clock 156 - "bus_slave" Slave AXI clock 157 - "slave_q2a" Slave Q2A clock 158 - "tbu" PCIe TBU clock 159 - "pipe" PIPE clock 160 161- clock-names: 162 Usage: required for sc8180x and sm8250 163 Value type: <stringlist> 164 Definition: Should contain the following entries 165 - "aux" Auxiliary clock 166 - "cfg" Configuration clock 167 - "bus_master" Master AXI clock 168 - "bus_slave" Slave AXI clock 169 - "slave_q2a" Slave Q2A clock 170 - "tbu" PCIe TBU clock 171 - "ddrss_sf_tbu" PCIe SF TBU clock 172 - "pipe" PIPE clock 173 174- clock-names: 175 Usage: required for sm8450-pcie0 and sm8450-pcie1 176 Value type: <stringlist> 177 Definition: Should contain the following entries 178 - "aux" Auxiliary clock 179 - "cfg" Configuration clock 180 - "bus_master" Master AXI clock 181 - "bus_slave" Slave AXI clock 182 - "slave_q2a" Slave Q2A clock 183 - "tbu" PCIe TBU clock 184 - "ddrss_sf_tbu" PCIe SF TBU clock 185 - "pipe" PIPE clock 186 - "pipe_mux" PIPE MUX 187 - "phy_pipe" PIPE output clock 188 - "ref" REFERENCE clock 189 - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 190 - "aggre1" Aggre NoC PCIe1 AXI clock 191 192- resets: 193 Usage: required 194 Value type: <prop-encoded-array> 195 Definition: List of phandle and reset specifier pairs as listed 196 in reset-names property 197 198- reset-names: 199 Usage: required for ipq/apq8064 200 Value type: <stringlist> 201 Definition: Should contain the following entries 202 - "axi" AXI reset 203 - "ahb" AHB reset 204 - "por" POR reset 205 - "pci" PCI reset 206 - "phy" PHY reset 207 208- reset-names: 209 Usage: required for apq8084 210 Value type: <stringlist> 211 Definition: Should contain the following entries 212 - "core" Core reset 213 214- reset-names: 215 Usage: required for ipq/apq8064 216 Value type: <stringlist> 217 Definition: Should contain the following entries 218 - "axi_m" AXI master reset 219 - "axi_s" AXI slave reset 220 - "pipe" PIPE reset 221 - "axi_m_vmid" VMID reset 222 - "axi_s_xpu" XPU reset 223 - "parf" PARF reset 224 - "phy" PHY reset 225 - "axi_m_sticky" AXI sticky reset 226 - "pipe_sticky" PIPE sticky reset 227 - "pwr" PWR reset 228 - "ahb" AHB reset 229 - "phy_ahb" PHY AHB reset 230 - "ext" EXT reset 231 232- reset-names: 233 Usage: required for ipq8074 234 Value type: <stringlist> 235 Definition: Should contain the following entries 236 - "pipe" PIPE reset 237 - "sleep" Sleep reset 238 - "sticky" Core Sticky reset 239 - "axi_m" AXI Master reset 240 - "axi_s" AXI Slave reset 241 - "ahb" AHB Reset 242 - "axi_m_sticky" AXI Master Sticky reset 243 244- reset-names: 245 Usage: required for ipq6018 246 Value type: <stringlist> 247 Definition: Should contain the following entries 248 - "pipe" PIPE reset 249 - "sleep" Sleep reset 250 - "sticky" Core Sticky reset 251 - "axi_m" AXI Master reset 252 - "axi_s" AXI Slave reset 253 - "ahb" AHB Reset 254 - "axi_m_sticky" AXI Master Sticky reset 255 - "axi_s_sticky" AXI Slave Sticky reset 256 257- reset-names: 258 Usage: required for qcs404 259 Value type: <stringlist> 260 Definition: Should contain the following entries 261 - "axi_m" AXI Master reset 262 - "axi_s" AXI Slave reset 263 - "axi_m_sticky" AXI Master Sticky reset 264 - "pipe_sticky" PIPE sticky reset 265 - "pwr" PWR reset 266 - "ahb" AHB reset 267 268- reset-names: 269 Usage: required for sc8180x, sdm845, sm8250 and sm8450 270 Value type: <stringlist> 271 Definition: Should contain the following entries 272 - "pci" PCIe core reset 273 274- power-domains: 275 Usage: required for apq8084 and msm8996/apq8096 276 Value type: <prop-encoded-array> 277 Definition: A phandle and power domain specifier pair to the 278 power domain which is responsible for collapsing 279 and restoring power to the peripheral 280 281- vdda-supply: 282 Usage: required 283 Value type: <phandle> 284 Definition: A phandle to the core analog power supply 285 286- vdda_phy-supply: 287 Usage: required for ipq/apq8064 288 Value type: <phandle> 289 Definition: A phandle to the analog power supply for PHY 290 291- vdda_refclk-supply: 292 Usage: required for ipq/apq8064 293 Value type: <phandle> 294 Definition: A phandle to the analog power supply for IC which generates 295 reference clock 296- vddpe-3v3-supply: 297 Usage: optional 298 Value type: <phandle> 299 Definition: A phandle to the PCIe endpoint power supply 300 301- phys: 302 Usage: required for apq8084 and qcs404 303 Value type: <phandle> 304 Definition: List of phandle(s) as listed in phy-names property 305 306- phy-names: 307 Usage: required for apq8084 and qcs404 308 Value type: <stringlist> 309 Definition: Should contain "pciephy" 310 311- <name>-gpios: 312 Usage: optional 313 Value type: <prop-encoded-array> 314 Definition: List of phandle and GPIO specifier pairs. Should contain 315 - "perst-gpios" PCIe endpoint reset signal line 316 - "wake-gpios" PCIe endpoint wake signal line 317 318* Example for ipq/apq8064 319 pcie@1b500000 { 320 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; 321 reg = <0x1b500000 0x1000 322 0x1b502000 0x80 323 0x1b600000 0x100 324 0x0ff00000 0x100000>; 325 reg-names = "dbi", "elbi", "parf", "config"; 326 device_type = "pci"; 327 linux,pci-domain = <0>; 328 bus-range = <0x00 0xff>; 329 num-lanes = <1>; 330 #address-cells = <3>; 331 #size-cells = <2>; 332 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ 333 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ 334 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; 335 interrupt-names = "msi"; 336 #interrupt-cells = <1>; 337 interrupt-map-mask = <0 0 0 0x7>; 338 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 339 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 340 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 341 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 342 clocks = <&gcc PCIE_A_CLK>, 343 <&gcc PCIE_H_CLK>, 344 <&gcc PCIE_PHY_CLK>, 345 <&gcc PCIE_AUX_CLK>, 346 <&gcc PCIE_ALT_REF_CLK>; 347 clock-names = "core", "iface", "phy", "aux", "ref"; 348 resets = <&gcc PCIE_ACLK_RESET>, 349 <&gcc PCIE_HCLK_RESET>, 350 <&gcc PCIE_POR_RESET>, 351 <&gcc PCIE_PCI_RESET>, 352 <&gcc PCIE_PHY_RESET>, 353 <&gcc PCIE_EXT_RESET>; 354 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 355 pinctrl-0 = <&pcie_pins_default>; 356 pinctrl-names = "default"; 357 }; 358 359* Example for apq8084 360 pcie0@fc520000 { 361 compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; 362 reg = <0xfc520000 0x2000>, 363 <0xff000000 0x1000>, 364 <0xff001000 0x1000>, 365 <0xff002000 0x2000>; 366 reg-names = "parf", "dbi", "elbi", "config"; 367 device_type = "pci"; 368 linux,pci-domain = <0>; 369 bus-range = <0x00 0xff>; 370 num-lanes = <1>; 371 #address-cells = <3>; 372 #size-cells = <2>; 373 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ 374 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ 375 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>; 376 interrupt-names = "msi"; 377 #interrupt-cells = <1>; 378 interrupt-map-mask = <0 0 0 0x7>; 379 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 380 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 381 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 382 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 383 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 384 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 385 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 386 <&gcc GCC_PCIE_0_AUX_CLK>; 387 clock-names = "iface", "master_bus", "slave_bus", "aux"; 388 resets = <&gcc GCC_PCIE_0_BCR>; 389 reset-names = "core"; 390 power-domains = <&gcc PCIE0_GDSC>; 391 vdda-supply = <&pma8084_l3>; 392 phys = <&pciephy0>; 393 phy-names = "pciephy"; 394 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; 395 pinctrl-0 = <&pcie0_pins_default>; 396 pinctrl-names = "default"; 397 }; 398