1* Qualcomm PCI express root complex 2 3- compatible: 4 Usage: required 5 Value type: <stringlist> 6 Definition: Value should contain 7 - "qcom,pcie-ipq8064" for ipq8064 8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 9 - "qcom,pcie-apq8064" for apq8064 10 - "qcom,pcie-apq8084" for apq8084 11 - "qcom,pcie-msm8996" for msm8996 or apq8096 12 - "qcom,pcie-ipq4019" for ipq4019 13 - "qcom,pcie-ipq8074" for ipq8074 14 - "qcom,pcie-qcs404" for qcs404 15 - "qcom,pcie-sdm845" for sdm845 16 - "qcom,pcie-sm8250" for sm8250 17 18- reg: 19 Usage: required 20 Value type: <prop-encoded-array> 21 Definition: Register ranges as listed in the reg-names property 22 23- reg-names: 24 Usage: required 25 Value type: <stringlist> 26 Definition: Must include the following entries 27 - "parf" Qualcomm specific registers 28 - "dbi" DesignWare PCIe registers 29 - "elbi" External local bus interface registers 30 - "config" PCIe configuration space 31 - "atu" ATU address space (optional) 32 33- device_type: 34 Usage: required 35 Value type: <string> 36 Definition: Should be "pci". As specified in designware-pcie.txt 37 38- #address-cells: 39 Usage: required 40 Value type: <u32> 41 Definition: Should be 3. As specified in designware-pcie.txt 42 43- #size-cells: 44 Usage: required 45 Value type: <u32> 46 Definition: Should be 2. As specified in designware-pcie.txt 47 48- ranges: 49 Usage: required 50 Value type: <prop-encoded-array> 51 Definition: As specified in designware-pcie.txt 52 53- interrupts: 54 Usage: required 55 Value type: <prop-encoded-array> 56 Definition: MSI interrupt 57 58- interrupt-names: 59 Usage: required 60 Value type: <stringlist> 61 Definition: Should contain "msi" 62 63- #interrupt-cells: 64 Usage: required 65 Value type: <u32> 66 Definition: Should be 1. As specified in designware-pcie.txt 67 68- interrupt-map-mask: 69 Usage: required 70 Value type: <prop-encoded-array> 71 Definition: As specified in designware-pcie.txt 72 73- interrupt-map: 74 Usage: required 75 Value type: <prop-encoded-array> 76 Definition: As specified in designware-pcie.txt 77 78- clocks: 79 Usage: required 80 Value type: <prop-encoded-array> 81 Definition: List of phandle and clock specifier pairs as listed 82 in clock-names property 83 84- clock-names: 85 Usage: required 86 Value type: <stringlist> 87 Definition: Should contain the following entries 88 - "iface" Configuration AHB clock 89 90- clock-names: 91 Usage: required for ipq/apq8064 92 Value type: <stringlist> 93 Definition: Should contain the following entries 94 - "core" Clocks the pcie hw block 95 - "phy" Clocks the pcie PHY block 96 - "aux" Clocks the pcie AUX block 97 - "ref" Clocks the pcie ref block 98- clock-names: 99 Usage: required for apq8084/ipq4019 100 Value type: <stringlist> 101 Definition: Should contain the following entries 102 - "aux" Auxiliary (AUX) clock 103 - "bus_master" Master AXI clock 104 - "bus_slave" Slave AXI clock 105 106- clock-names: 107 Usage: required for msm8996/apq8096 108 Value type: <stringlist> 109 Definition: Should contain the following entries 110 - "pipe" Pipe Clock driving internal logic 111 - "aux" Auxiliary (AUX) clock 112 - "cfg" Configuration clock 113 - "bus_master" Master AXI clock 114 - "bus_slave" Slave AXI clock 115 116- clock-names: 117 Usage: required for ipq8074 118 Value type: <stringlist> 119 Definition: Should contain the following entries 120 - "iface" PCIe to SysNOC BIU clock 121 - "axi_m" AXI Master clock 122 - "axi_s" AXI Slave clock 123 - "ahb" AHB clock 124 - "aux" Auxiliary clock 125 126- clock-names: 127 Usage: required for qcs404 128 Value type: <stringlist> 129 Definition: Should contain the following entries 130 - "iface" AHB clock 131 - "aux" Auxiliary clock 132 - "master_bus" AXI Master clock 133 - "slave_bus" AXI Slave clock 134 135- clock-names: 136 Usage: required for sdm845 137 Value type: <stringlist> 138 Definition: Should contain the following entries 139 - "aux" Auxiliary clock 140 - "cfg" Configuration clock 141 - "bus_master" Master AXI clock 142 - "bus_slave" Slave AXI clock 143 - "slave_q2a" Slave Q2A clock 144 - "tbu" PCIe TBU clock 145 - "pipe" PIPE clock 146 147- clock-names: 148 Usage: required for sm8250 149 Value type: <stringlist> 150 Definition: Should contain the following entries 151 - "aux" Auxiliary clock 152 - "cfg" Configuration clock 153 - "bus_master" Master AXI clock 154 - "bus_slave" Slave AXI clock 155 - "slave_q2a" Slave Q2A clock 156 - "tbu" PCIe TBU clock 157 - "ddrss_sf_tbu" PCIe SF TBU clock 158 - "pipe" PIPE clock 159 160- resets: 161 Usage: required 162 Value type: <prop-encoded-array> 163 Definition: List of phandle and reset specifier pairs as listed 164 in reset-names property 165 166- reset-names: 167 Usage: required for ipq/apq8064 168 Value type: <stringlist> 169 Definition: Should contain the following entries 170 - "axi" AXI reset 171 - "ahb" AHB reset 172 - "por" POR reset 173 - "pci" PCI reset 174 - "phy" PHY reset 175 176- reset-names: 177 Usage: required for apq8084 178 Value type: <stringlist> 179 Definition: Should contain the following entries 180 - "core" Core reset 181 182- reset-names: 183 Usage: required for ipq/apq8064 184 Value type: <stringlist> 185 Definition: Should contain the following entries 186 - "axi_m" AXI master reset 187 - "axi_s" AXI slave reset 188 - "pipe" PIPE reset 189 - "axi_m_vmid" VMID reset 190 - "axi_s_xpu" XPU reset 191 - "parf" PARF reset 192 - "phy" PHY reset 193 - "axi_m_sticky" AXI sticky reset 194 - "pipe_sticky" PIPE sticky reset 195 - "pwr" PWR reset 196 - "ahb" AHB reset 197 - "phy_ahb" PHY AHB reset 198 - "ext" EXT reset 199 200- reset-names: 201 Usage: required for ipq8074 202 Value type: <stringlist> 203 Definition: Should contain the following entries 204 - "pipe" PIPE reset 205 - "sleep" Sleep reset 206 - "sticky" Core Sticky reset 207 - "axi_m" AXI Master reset 208 - "axi_s" AXI Slave reset 209 - "ahb" AHB Reset 210 - "axi_m_sticky" AXI Master Sticky reset 211 212- reset-names: 213 Usage: required for qcs404 214 Value type: <stringlist> 215 Definition: Should contain the following entries 216 - "axi_m" AXI Master reset 217 - "axi_s" AXI Slave reset 218 - "axi_m_sticky" AXI Master Sticky reset 219 - "pipe_sticky" PIPE sticky reset 220 - "pwr" PWR reset 221 - "ahb" AHB reset 222 223- reset-names: 224 Usage: required for sdm845 and sm8250 225 Value type: <stringlist> 226 Definition: Should contain the following entries 227 - "pci" PCIe core reset 228 229- power-domains: 230 Usage: required for apq8084 and msm8996/apq8096 231 Value type: <prop-encoded-array> 232 Definition: A phandle and power domain specifier pair to the 233 power domain which is responsible for collapsing 234 and restoring power to the peripheral 235 236- vdda-supply: 237 Usage: required 238 Value type: <phandle> 239 Definition: A phandle to the core analog power supply 240 241- vdda_phy-supply: 242 Usage: required for ipq/apq8064 243 Value type: <phandle> 244 Definition: A phandle to the analog power supply for PHY 245 246- vdda_refclk-supply: 247 Usage: required for ipq/apq8064 248 Value type: <phandle> 249 Definition: A phandle to the analog power supply for IC which generates 250 reference clock 251- vddpe-3v3-supply: 252 Usage: optional 253 Value type: <phandle> 254 Definition: A phandle to the PCIe endpoint power supply 255 256- phys: 257 Usage: required for apq8084 and qcs404 258 Value type: <phandle> 259 Definition: List of phandle(s) as listed in phy-names property 260 261- phy-names: 262 Usage: required for apq8084 and qcs404 263 Value type: <stringlist> 264 Definition: Should contain "pciephy" 265 266- <name>-gpios: 267 Usage: optional 268 Value type: <prop-encoded-array> 269 Definition: List of phandle and GPIO specifier pairs. Should contain 270 - "perst-gpios" PCIe endpoint reset signal line 271 - "wake-gpios" PCIe endpoint wake signal line 272 273* Example for ipq/apq8064 274 pcie@1b500000 { 275 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; 276 reg = <0x1b500000 0x1000 277 0x1b502000 0x80 278 0x1b600000 0x100 279 0x0ff00000 0x100000>; 280 reg-names = "dbi", "elbi", "parf", "config"; 281 device_type = "pci"; 282 linux,pci-domain = <0>; 283 bus-range = <0x00 0xff>; 284 num-lanes = <1>; 285 #address-cells = <3>; 286 #size-cells = <2>; 287 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ 288 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ 289 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; 290 interrupt-names = "msi"; 291 #interrupt-cells = <1>; 292 interrupt-map-mask = <0 0 0 0x7>; 293 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 294 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 295 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 296 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 297 clocks = <&gcc PCIE_A_CLK>, 298 <&gcc PCIE_H_CLK>, 299 <&gcc PCIE_PHY_CLK>, 300 <&gcc PCIE_AUX_CLK>, 301 <&gcc PCIE_ALT_REF_CLK>; 302 clock-names = "core", "iface", "phy", "aux", "ref"; 303 resets = <&gcc PCIE_ACLK_RESET>, 304 <&gcc PCIE_HCLK_RESET>, 305 <&gcc PCIE_POR_RESET>, 306 <&gcc PCIE_PCI_RESET>, 307 <&gcc PCIE_PHY_RESET>, 308 <&gcc PCIE_EXT_RESET>; 309 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 310 pinctrl-0 = <&pcie_pins_default>; 311 pinctrl-names = "default"; 312 }; 313 314* Example for apq8084 315 pcie0@fc520000 { 316 compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; 317 reg = <0xfc520000 0x2000>, 318 <0xff000000 0x1000>, 319 <0xff001000 0x1000>, 320 <0xff002000 0x2000>; 321 reg-names = "parf", "dbi", "elbi", "config"; 322 device_type = "pci"; 323 linux,pci-domain = <0>; 324 bus-range = <0x00 0xff>; 325 num-lanes = <1>; 326 #address-cells = <3>; 327 #size-cells = <2>; 328 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ 329 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ 330 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>; 331 interrupt-names = "msi"; 332 #interrupt-cells = <1>; 333 interrupt-map-mask = <0 0 0 0x7>; 334 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 335 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 336 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 337 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 338 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 339 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 340 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 341 <&gcc GCC_PCIE_0_AUX_CLK>; 342 clock-names = "iface", "master_bus", "slave_bus", "aux"; 343 resets = <&gcc GCC_PCIE_0_BCR>; 344 reset-names = "core"; 345 power-domains = <&gcc PCIE0_GDSC>; 346 vdda-supply = <&pma8084_l3>; 347 phys = <&pciephy0>; 348 phy-names = "pciephy"; 349 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; 350 pinctrl-0 = <&pcie0_pins_default>; 351 pinctrl-names = "default"; 352 }; 353