xref: /freebsd/sys/contrib/device-tree/Bindings/pci/qcom,pcie-ep.yaml (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm PCIe Endpoint Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,sdx55-pcie-ep
16      - qcom,sm8450-pcie-ep
17
18  reg:
19    items:
20      - description: Qualcomm-specific PARF configuration registers
21      - description: DesignWare PCIe registers
22      - description: External local bus interface registers
23      - description: Address Translation Unit (ATU) registers
24      - description: Memory region used to map remote RC address space
25      - description: BAR memory region
26
27  reg-names:
28    items:
29      - const: parf
30      - const: dbi
31      - const: elbi
32      - const: atu
33      - const: addr_space
34      - const: mmio
35
36  clocks:
37    minItems: 7
38    maxItems: 8
39
40  clock-names:
41    minItems: 7
42    maxItems: 8
43
44  qcom,perst-regs:
45    description: Reference to a syscon representing TCSR followed by the two
46                 offsets within syscon for Perst enable and Perst separation
47                 enable registers
48    $ref: /schemas/types.yaml#/definitions/phandle-array
49    items:
50      - items:
51          - description: Syscon to TCSR system registers
52          - description: Perst enable offset
53          - description: Perst separation enable offset
54
55  interrupts:
56    items:
57      - description: PCIe Global interrupt
58      - description: PCIe Doorbell interrupt
59
60  interrupt-names:
61    items:
62      - const: global
63      - const: doorbell
64
65  reset-gpios:
66    description: GPIO used as PERST# input signal
67    maxItems: 1
68
69  wake-gpios:
70    description: GPIO used as WAKE# output signal
71    maxItems: 1
72
73  resets:
74    maxItems: 1
75
76  reset-names:
77    const: core
78
79  power-domains:
80    maxItems: 1
81
82  phys:
83    maxItems: 1
84
85  phy-names:
86    const: pciephy
87
88  num-lanes:
89    default: 2
90
91required:
92  - compatible
93  - reg
94  - reg-names
95  - clocks
96  - clock-names
97  - interrupts
98  - interrupt-names
99  - reset-gpios
100  - resets
101  - reset-names
102  - power-domains
103
104allOf:
105  - $ref: pci-ep.yaml#
106  - if:
107      properties:
108        compatible:
109          contains:
110            enum:
111              - qcom,sdx55-pcie-ep
112    then:
113      properties:
114        clocks:
115          items:
116            - description: PCIe Auxiliary clock
117            - description: PCIe CFG AHB clock
118            - description: PCIe Master AXI clock
119            - description: PCIe Slave AXI clock
120            - description: PCIe Slave Q2A AXI clock
121            - description: PCIe Sleep clock
122            - description: PCIe Reference clock
123        clock-names:
124          items:
125            - const: aux
126            - const: cfg
127            - const: bus_master
128            - const: bus_slave
129            - const: slave_q2a
130            - const: sleep
131            - const: ref
132
133  - if:
134      properties:
135        compatible:
136          contains:
137            enum:
138              - qcom,sm8450-pcie-ep
139    then:
140      properties:
141        clocks:
142          items:
143            - description: PCIe Auxiliary clock
144            - description: PCIe CFG AHB clock
145            - description: PCIe Master AXI clock
146            - description: PCIe Slave AXI clock
147            - description: PCIe Slave Q2A AXI clock
148            - description: PCIe Reference clock
149            - description: PCIe DDRSS SF TBU clock
150            - description: PCIe AGGRE NOC AXI clock
151        clock-names:
152          items:
153            - const: aux
154            - const: cfg
155            - const: bus_master
156            - const: bus_slave
157            - const: slave_q2a
158            - const: ref
159            - const: ddrss_sf_tbu
160            - const: aggre_noc_axi
161
162unevaluatedProperties: false
163
164examples:
165  - |
166    #include <dt-bindings/clock/qcom,gcc-sdx55.h>
167    #include <dt-bindings/gpio/gpio.h>
168    #include <dt-bindings/interrupt-controller/arm-gic.h>
169    pcie_ep: pcie-ep@1c00000 {
170        compatible = "qcom,sdx55-pcie-ep";
171        reg = <0x01c00000 0x3000>,
172              <0x40000000 0xf1d>,
173              <0x40000f20 0xc8>,
174              <0x40001000 0x1000>,
175              <0x40002000 0x1000>,
176              <0x01c03000 0x3000>;
177        reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
178                    "mmio";
179
180        clocks = <&gcc GCC_PCIE_AUX_CLK>,
181             <&gcc GCC_PCIE_CFG_AHB_CLK>,
182             <&gcc GCC_PCIE_MSTR_AXI_CLK>,
183             <&gcc GCC_PCIE_SLV_AXI_CLK>,
184             <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
185             <&gcc GCC_PCIE_SLEEP_CLK>,
186             <&gcc GCC_PCIE_0_CLKREF_CLK>;
187        clock-names = "aux", "cfg", "bus_master", "bus_slave",
188                      "slave_q2a", "sleep", "ref";
189
190        qcom,perst-regs = <&tcsr 0xb258 0xb270>;
191
192        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
193                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
194        interrupt-names = "global", "doorbell";
195        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
196        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
197        resets = <&gcc GCC_PCIE_BCR>;
198        reset-names = "core";
199        power-domains = <&gcc PCIE_GDSC>;
200        phys = <&pcie0_lane>;
201        phy-names = "pciephy";
202        max-link-speed = <3>;
203        num-lanes = <2>;
204    };
205