xref: /freebsd/sys/contrib/device-tree/Bindings/pci/qcom,pcie-ep.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm PCIe Endpoint Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12properties:
13  compatible:
14    enum:
15      - qcom,sdx55-pcie-ep
16      - qcom,sdx65-pcie-ep
17      - qcom,sm8450-pcie-ep
18
19  reg:
20    items:
21      - description: Qualcomm-specific PARF configuration registers
22      - description: DesignWare PCIe registers
23      - description: External local bus interface registers
24      - description: Address Translation Unit (ATU) registers
25      - description: Memory region used to map remote RC address space
26      - description: BAR memory region
27
28  reg-names:
29    items:
30      - const: parf
31      - const: dbi
32      - const: elbi
33      - const: atu
34      - const: addr_space
35      - const: mmio
36
37  clocks:
38    minItems: 7
39    maxItems: 8
40
41  clock-names:
42    minItems: 7
43    maxItems: 8
44
45  qcom,perst-regs:
46    description: Reference to a syscon representing TCSR followed by the two
47                 offsets within syscon for Perst enable and Perst separation
48                 enable registers
49    $ref: /schemas/types.yaml#/definitions/phandle-array
50    items:
51      - items:
52          - description: Syscon to TCSR system registers
53          - description: Perst enable offset
54          - description: Perst separation enable offset
55
56  interrupts:
57    items:
58      - description: PCIe Global interrupt
59      - description: PCIe Doorbell interrupt
60
61  interrupt-names:
62    items:
63      - const: global
64      - const: doorbell
65
66  reset-gpios:
67    description: GPIO used as PERST# input signal
68    maxItems: 1
69
70  wake-gpios:
71    description: GPIO used as WAKE# output signal
72    maxItems: 1
73
74  resets:
75    maxItems: 1
76
77  reset-names:
78    const: core
79
80  power-domains:
81    maxItems: 1
82
83  phys:
84    maxItems: 1
85
86  phy-names:
87    const: pciephy
88
89  num-lanes:
90    default: 2
91
92required:
93  - compatible
94  - reg
95  - reg-names
96  - clocks
97  - clock-names
98  - interrupts
99  - interrupt-names
100  - reset-gpios
101  - resets
102  - reset-names
103  - power-domains
104
105allOf:
106  - $ref: pci-ep.yaml#
107  - if:
108      properties:
109        compatible:
110          contains:
111            enum:
112              - qcom,sdx55-pcie-ep
113              - qcom,sdx65-pcie-ep
114    then:
115      properties:
116        clocks:
117          items:
118            - description: PCIe Auxiliary clock
119            - description: PCIe CFG AHB clock
120            - description: PCIe Master AXI clock
121            - description: PCIe Slave AXI clock
122            - description: PCIe Slave Q2A AXI clock
123            - description: PCIe Sleep clock
124            - description: PCIe Reference clock
125        clock-names:
126          items:
127            - const: aux
128            - const: cfg
129            - const: bus_master
130            - const: bus_slave
131            - const: slave_q2a
132            - const: sleep
133            - const: ref
134
135  - if:
136      properties:
137        compatible:
138          contains:
139            enum:
140              - qcom,sm8450-pcie-ep
141    then:
142      properties:
143        clocks:
144          items:
145            - description: PCIe Auxiliary clock
146            - description: PCIe CFG AHB clock
147            - description: PCIe Master AXI clock
148            - description: PCIe Slave AXI clock
149            - description: PCIe Slave Q2A AXI clock
150            - description: PCIe Reference clock
151            - description: PCIe DDRSS SF TBU clock
152            - description: PCIe AGGRE NOC AXI clock
153        clock-names:
154          items:
155            - const: aux
156            - const: cfg
157            - const: bus_master
158            - const: bus_slave
159            - const: slave_q2a
160            - const: ref
161            - const: ddrss_sf_tbu
162            - const: aggre_noc_axi
163
164unevaluatedProperties: false
165
166examples:
167  - |
168    #include <dt-bindings/clock/qcom,gcc-sdx55.h>
169    #include <dt-bindings/gpio/gpio.h>
170    #include <dt-bindings/interrupt-controller/arm-gic.h>
171    pcie_ep: pcie-ep@1c00000 {
172        compatible = "qcom,sdx55-pcie-ep";
173        reg = <0x01c00000 0x3000>,
174              <0x40000000 0xf1d>,
175              <0x40000f20 0xc8>,
176              <0x40001000 0x1000>,
177              <0x40002000 0x1000>,
178              <0x01c03000 0x3000>;
179        reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
180                    "mmio";
181
182        clocks = <&gcc GCC_PCIE_AUX_CLK>,
183             <&gcc GCC_PCIE_CFG_AHB_CLK>,
184             <&gcc GCC_PCIE_MSTR_AXI_CLK>,
185             <&gcc GCC_PCIE_SLV_AXI_CLK>,
186             <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
187             <&gcc GCC_PCIE_SLEEP_CLK>,
188             <&gcc GCC_PCIE_0_CLKREF_CLK>;
189        clock-names = "aux", "cfg", "bus_master", "bus_slave",
190                      "slave_q2a", "sleep", "ref";
191
192        qcom,perst-regs = <&tcsr 0xb258 0xb270>;
193
194        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
195                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
196        interrupt-names = "global", "doorbell";
197        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
198        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
199        resets = <&gcc GCC_PCIE_BCR>;
200        reset-names = "core";
201        power-domains = <&gcc PCIE_GDSC>;
202        phys = <&pcie0_lane>;
203        phy-names = "pciephy";
204        max-link-speed = <3>;
205        num-lanes = <2>;
206    };
207