1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 13 14description: | 15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of 17 the controller instances are dual mode where in they can work either in 18 Root Port mode or Endpoint mode but one at a time. 19 20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 21 tree bindings. 22 23properties: 24 compatible: 25 enum: 26 - nvidia,tegra194-pcie 27 - nvidia,tegra234-pcie 28 29 reg: 30 items: 31 - description: controller's application logic registers 32 - description: configuration registers 33 - description: iATU and DMA registers. This is where the iATU (internal 34 Address Translation Unit) registers of the PCIe core are made 35 available for software access. 36 - description: aperture where the Root Port's own configuration 37 registers are available. 38 39 reg-names: 40 items: 41 - const: appl 42 - const: config 43 - const: atu_dma 44 - const: dbi 45 46 interrupts: 47 items: 48 - description: controller interrupt 49 - description: MSI interrupt 50 51 interrupt-names: 52 items: 53 - const: intr 54 - const: msi 55 56 clocks: 57 items: 58 - description: module clock 59 60 clock-names: 61 items: 62 - const: core 63 64 resets: 65 items: 66 - description: APB bus interface reset 67 - description: module reset 68 69 reset-names: 70 items: 71 - const: apb 72 - const: core 73 74 phys: 75 minItems: 1 76 maxItems: 8 77 78 phy-names: 79 minItems: 1 80 items: 81 - const: p2u-0 82 - const: p2u-1 83 - const: p2u-2 84 - const: p2u-3 85 - const: p2u-4 86 - const: p2u-5 87 - const: p2u-6 88 - const: p2u-7 89 90 power-domains: 91 maxItems: 1 92 description: | 93 A phandle to the node that controls power to the respective PCIe 94 controller and a specifier name for the PCIe controller. 95 96 Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h" 97 Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h" 98 99 interconnects: 100 items: 101 - description: memory read client 102 - description: memory write client 103 104 interconnect-names: 105 items: 106 - const: dma-mem # read 107 - const: write 108 109 dma-coherent: true 110 111 nvidia,bpmp: 112 $ref: /schemas/types.yaml#/definitions/phandle-array 113 description: | 114 Must contain a pair of phandles to BPMP controller node followed by 115 controller ID. Following are the controller IDs for each controller: 116 117 Tegra194 118 119 0: C0 120 1: C1 121 2: C2 122 3: C3 123 4: C4 124 5: C5 125 126 Tegra234 127 128 0 : C0 129 1 : C1 130 2 : C2 131 3 : C3 132 4 : C4 133 5 : C5 134 6 : C6 135 7 : C7 136 8 : C8 137 9 : C9 138 10: C10 139 140 items: 141 - items: 142 - description: phandle to BPMP controller node 143 - description: PCIe controller ID 144 maximum: 10 145 146 nvidia,update-fc-fixup: 147 description: | 148 This is a boolean property and needs to be present to improve performance 149 when a platform is designed in such a way that it satisfies at least one 150 of the following conditions thereby enabling Root Port to exchange 151 optimum number of FC (Flow Control) credits with downstream devices: 152 153 NOTE: This is applicable only for Tegra194. 154 155 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 156 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 157 a) speed is Gen-2 and MPS is 256B 158 b) speed is >= Gen-3 with any MPS 159 160 $ref: /schemas/types.yaml#/definitions/flag 161 162 nvidia,aspm-cmrt-us: 163 description: Common Mode Restore Time for proper operation of ASPM to be 164 specified in microseconds 165 166 nvidia,aspm-pwr-on-t-us: 167 description: Power On time for proper operation of ASPM to be specified in 168 microseconds 169 170 nvidia,aspm-l0s-entrance-latency-us: 171 description: ASPM L0s entrance latency to be specified in microseconds 172 173 vddio-pex-ctl-supply: 174 description: A phandle to the regulator supply for PCIe side band signals. 175 176 vpcie3v3-supply: 177 description: A phandle to the regulator node that supplies 3.3V to the slot 178 if the platform has one such slot, e.g., x16 slot owned by C5 controller 179 in p2972-0000 platform. 180 181 vpcie12v-supply: 182 description: A phandle to the regulator node that supplies 12V to the slot 183 if the platform has one such slot, e.g., x16 slot owned by C5 controller 184 in p2972-0000 platform. 185 186 nvidia,enable-srns: 187 description: | 188 This boolean property needs to be present if the controller is 189 configured to operate in SRNS (Separate Reference Clocks with No 190 Spread-Spectrum Clocking). NOTE: This is applicable only for 191 Tegra234. 192 193 $ref: /schemas/types.yaml#/definitions/flag 194 195 nvidia,enable-ext-refclk: 196 description: | 197 This boolean property needs to be present if the controller is 198 configured to use the reference clocking coming in from an external 199 clock source instead of using the internal clock source. 200 201 $ref: /schemas/types.yaml#/definitions/flag 202 203allOf: 204 - $ref: /schemas/pci/snps,dw-pcie.yaml# 205 206unevaluatedProperties: false 207 208required: 209 - interrupts 210 - interrupt-names 211 - interrupt-map 212 - interrupt-map-mask 213 - clocks 214 - clock-names 215 - resets 216 - reset-names 217 - power-domains 218 - vddio-pex-ctl-supply 219 - num-lanes 220 - phys 221 - phy-names 222 - nvidia,bpmp 223 224examples: 225 - | 226 #include <dt-bindings/clock/tegra194-clock.h> 227 #include <dt-bindings/interrupt-controller/arm-gic.h> 228 #include <dt-bindings/power/tegra194-powergate.h> 229 #include <dt-bindings/reset/tegra194-reset.h> 230 231 bus@0 { 232 #address-cells = <2>; 233 #size-cells = <2>; 234 ranges = <0x0 0x0 0x0 0x8 0x0>; 235 236 pcie@14180000 { 237 compatible = "nvidia,tegra194-pcie"; 238 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 239 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 240 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 241 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 242 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 243 reg-names = "appl", "config", "atu_dma", "dbi"; 244 245 #address-cells = <3>; 246 #size-cells = <2>; 247 device_type = "pci"; 248 num-lanes = <8>; 249 linux,pci-domain = <0>; 250 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 253 254 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 255 clock-names = "core"; 256 257 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 258 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 259 reset-names = "apb", "core"; 260 261 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 262 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 263 interrupt-names = "intr", "msi"; 264 265 #interrupt-cells = <1>; 266 interrupt-map-mask = <0 0 0 0>; 267 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 268 269 nvidia,bpmp = <&bpmp 0>; 270 271 supports-clkreq; 272 nvidia,aspm-cmrt-us = <60>; 273 nvidia,aspm-pwr-on-t-us = <20>; 274 nvidia,aspm-l0s-entrance-latency-us = <3>; 275 276 bus-range = <0x0 0xff>; 277 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */ 278 <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */ 279 <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */ 280 281 vddio-pex-ctl-supply = <&vdd_1v8ao>; 282 vpcie3v3-supply = <&vdd_3v3_pcie>; 283 vpcie12v-supply = <&vdd_12v_pcie>; 284 285 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 286 <&p2u_hsio_5>; 287 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 288 }; 289 }; 290 291 - | 292 #include <dt-bindings/clock/tegra234-clock.h> 293 #include <dt-bindings/interrupt-controller/arm-gic.h> 294 #include <dt-bindings/power/tegra234-powergate.h> 295 #include <dt-bindings/reset/tegra234-reset.h> 296 297 bus@0 { 298 #address-cells = <2>; 299 #size-cells = <2>; 300 ranges = <0x0 0x0 0x0 0x8 0x0>; 301 302 pcie@14160000 { 303 compatible = "nvidia,tegra234-pcie"; 304 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 305 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 306 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 307 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 308 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 309 reg-names = "appl", "config", "atu_dma", "dbi"; 310 311 #address-cells = <3>; 312 #size-cells = <2>; 313 device_type = "pci"; 314 num-lanes = <4>; 315 num-viewport = <8>; 316 linux,pci-domain = <4>; 317 318 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 319 clock-names = "core"; 320 321 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 322 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 323 reset-names = "apb", "core"; 324 325 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 326 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 327 interrupt-names = "intr", "msi"; 328 329 #interrupt-cells = <1>; 330 interrupt-map-mask = <0 0 0 0>; 331 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 332 333 nvidia,bpmp = <&bpmp 4>; 334 335 nvidia,aspm-cmrt-us = <60>; 336 nvidia,aspm-pwr-on-t-us = <20>; 337 nvidia,aspm-l0s-entrance-latency-us = <3>; 338 339 bus-range = <0x0 0xff>; 340 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */ 341 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */ 342 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */ 343 344 vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>; 345 346 phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, 347 <&p2u_hsio_7>; 348 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 349 }; 350 }; 351