1NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) 2 3This PCIe controller is based on the Synopsis Designware PCIe IP 4and thus inherits all the common properties defined in designware-pcie.txt. 5Some of the controller instances are dual mode where in they can work either 6in root port mode or endpoint mode but one at a time. 7 8Required properties: 9- power-domains: A phandle to the node that controls power to the respective 10 PCIe controller and a specifier name for the PCIe controller. Following are 11 the specifiers for the different PCIe controllers 12 TEGRA194_POWER_DOMAIN_PCIEX8B: C0 13 TEGRA194_POWER_DOMAIN_PCIEX1A: C1 14 TEGRA194_POWER_DOMAIN_PCIEX1A: C2 15 TEGRA194_POWER_DOMAIN_PCIEX1A: C3 16 TEGRA194_POWER_DOMAIN_PCIEX4A: C4 17 TEGRA194_POWER_DOMAIN_PCIEX8A: C5 18 these specifiers are defined in 19 "include/dt-bindings/power/tegra194-powergate.h" file. 20- reg: A list of physical base address and length pairs for each set of 21 controller registers. Must contain an entry for each entry in the reg-names 22 property. 23- reg-names: Must include the following entries: 24 "appl": Controller's application logic registers 25 "config": As per the definition in designware-pcie.txt 26 "atu_dma": iATU and DMA registers. This is where the iATU (internal Address 27 Translation Unit) registers of the PCIe core are made available 28 for SW access. 29 "dbi": The aperture where root port's own configuration registers are 30 available 31- interrupts: A list of interrupt outputs of the controller. Must contain an 32 entry for each entry in the interrupt-names property. 33- interrupt-names: Must include the following entries: 34 "intr": The Tegra interrupt that is asserted for controller interrupts 35- clocks: Must contain an entry for each entry in clock-names. 36 See ../clocks/clock-bindings.txt for details. 37- clock-names: Must include the following entries: 38 - core 39- resets: Must contain an entry for each entry in reset-names. 40 See ../reset/reset.txt for details. 41- reset-names: Must include the following entries: 42 - apb 43 - core 44- phys: Must contain a phandle to P2U PHY for each entry in phy-names. 45- phy-names: Must include an entry for each active lane. 46 "p2u-N": where N ranges from 0 to one less than the total number of lanes 47- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed 48 by controller-id. Following are the controller ids for each controller. 49 0: C0 50 1: C1 51 2: C2 52 3: C3 53 4: C4 54 5: C5 55- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals 56 57RC mode: 58- compatible: Tegra19x must contain "nvidia,tegra194-pcie" 59- device_type: Must be "pci" for RC mode 60- interrupt-names: Must include the following entries: 61 "msi": The Tegra interrupt that is asserted when an MSI is received 62- bus-range: Range of bus numbers associated with this controller 63- #address-cells: Address representation for root ports (must be 3) 64 - cell 0 specifies the bus and device numbers of the root port: 65 [23:16]: bus number 66 [15:11]: device number 67 - cell 1 denotes the upper 32 address bits and should be 0 68 - cell 2 contains the lower 32 address bits and is used to translate to the 69 CPU address space 70- #size-cells: Size representation for root ports (must be 2) 71- ranges: Describes the translation of addresses for root ports and standard 72 PCI regions. The entries must be 7 cells each, where the first three cells 73 correspond to the address as described for the #address-cells property 74 above, the fourth and fifth cells are for the physical CPU address to 75 translate to and the sixth and seventh cells are as described for the 76 #size-cells property above. 77 - Entries setup the mapping for the standard I/O, memory and 78 prefetchable PCI regions. The first cell determines the type of region 79 that is setup: 80 - 0x81000000: I/O memory region 81 - 0x82000000: non-prefetchable memory region 82 - 0xc2000000: prefetchable memory region 83 Please refer to the standard PCI bus binding document for a more detailed 84 explanation. 85- #interrupt-cells: Size representation for interrupts (must be 1) 86- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 87 Please refer to the standard PCI bus binding document for a more detailed 88 explanation. 89 90EP mode: 91In Tegra194, Only controllers C0, C4 & C5 support EP mode. 92- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep" 93- reg-names: Must include the following entries: 94 "addr_space": Used to map remote RC address space 95- reset-gpios: Must contain a phandle to a GPIO controller followed by 96 GPIO that is being used as PERST input signal. Please refer to pci.txt 97 document. 98 99Optional properties: 100- pinctrl-names: A list of pinctrl state names. 101 It is mandatory for C5 controller and optional for other controllers. 102 - "default": Configures PCIe I/O for proper operation. 103- pinctrl-0: phandle for the 'default' state of pin configuration. 104 It is mandatory for C5 controller and optional for other controllers. 105- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt 106- nvidia,update-fc-fixup: This is a boolean property and needs to be present to 107 improve performance when a platform is designed in such a way that it 108 satisfies at least one of the following conditions thereby enabling root 109 port to exchange optimum number of FC (Flow Control) credits with 110 downstream devices 111 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 112 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 113 a) speed is Gen-2 and MPS is 256B 114 b) speed is >= Gen-3 with any MPS 115- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM 116 to be specified in microseconds 117- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be 118 specified in microseconds 119- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be 120 specified in microseconds 121 122RC mode: 123- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot 124 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 125 in p2972-0000 platform). 126- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot 127 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 128 in p2972-0000 platform). 129 130EP mode: 131- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller 132 followed by GPIO that is being used to enable REFCLK to controller from host 133 134NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 135operate in the endpoint mode because of the way the platform is designed. 136 137Examples: 138========= 139 140Tegra194 RC mode: 141----------------- 142 143 pcie@14180000 { 144 compatible = "nvidia,tegra194-pcie"; 145 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 146 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 147 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 148 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */ 149 reg-names = "appl", "config", "atu_dma"; 150 151 #address-cells = <3>; 152 #size-cells = <2>; 153 device_type = "pci"; 154 num-lanes = <8>; 155 linux,pci-domain = <0>; 156 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 159 160 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 161 clock-names = "core"; 162 163 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 164 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 165 reset-names = "apb", "core"; 166 167 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 168 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 169 interrupt-names = "intr", "msi"; 170 171 #interrupt-cells = <1>; 172 interrupt-map-mask = <0 0 0 0>; 173 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 174 175 nvidia,bpmp = <&bpmp 0>; 176 177 supports-clkreq; 178 nvidia,aspm-cmrt-us = <60>; 179 nvidia,aspm-pwr-on-t-us = <20>; 180 nvidia,aspm-l0s-entrance-latency-us = <3>; 181 182 bus-range = <0x0 0xff>; 183 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 184 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */ 185 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ 186 187 vddio-pex-ctl-supply = <&vdd_1v8ao>; 188 vpcie3v3-supply = <&vdd_3v3_pcie>; 189 vpcie12v-supply = <&vdd_12v_pcie>; 190 191 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 192 <&p2u_hsio_5>; 193 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 194 }; 195 196Tegra194 EP mode: 197----------------- 198 199 pcie_ep@141a0000 { 200 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 201 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 202 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 203 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 204 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ 205 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 206 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 207 208 num-lanes = <8>; 209 num-ib-windows = <2>; 210 num-ob-windows = <8>; 211 212 pinctrl-names = "default"; 213 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 214 215 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 216 clock-names = "core"; 217 218 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 219 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 220 reset-names = "apb", "core"; 221 222 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 223 interrupt-names = "intr"; 224 225 nvidia,bpmp = <&bpmp 5>; 226 227 nvidia,aspm-cmrt-us = <60>; 228 nvidia,aspm-pwr-on-t-us = <20>; 229 nvidia,aspm-l0s-entrance-latency-us = <3>; 230 231 vddio-pex-ctl-supply = <&vdd_1v8ao>; 232 233 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 234 235 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 236 GPIO_ACTIVE_HIGH>; 237 238 phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 239 <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 240 <&p2u_nvhs_6>, <&p2u_nvhs_7>; 241 242 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 243 "p2u-5", "p2u-6", "p2u-7"; 244 }; 245