1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 13 14description: | 15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 17 of the controller instances are dual mode; they can work either in Root 18 Port mode or Endpoint mode but one at a time. 19 20 On Tegra194, controllers C0, C4 and C5 support Endpoint mode. 21 On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode. 22 23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 24 operate in the Endpoint mode because of the way the platform is designed. 25 26properties: 27 compatible: 28 enum: 29 - nvidia,tegra194-pcie-ep 30 - nvidia,tegra234-pcie-ep 31 32 reg: 33 items: 34 - description: controller's application logic registers 35 - description: iATU and DMA registers. This is where the iATU (internal 36 Address Translation Unit) registers of the PCIe core are made 37 available for software access. 38 - description: aperture where the Root Port's own configuration 39 registers are available. 40 - description: aperture used to map the remote Root Complex address space 41 42 reg-names: 43 items: 44 - const: appl 45 - const: atu_dma 46 - const: dbi 47 - const: addr_space 48 49 interrupts: 50 items: 51 - description: controller interrupt 52 53 interrupt-names: 54 items: 55 - const: intr 56 57 clocks: 58 items: 59 - description: module clock 60 61 clock-names: 62 items: 63 - const: core 64 65 resets: 66 items: 67 - description: APB bus interface reset 68 - description: module reset 69 70 reset-names: 71 items: 72 - const: apb 73 - const: core 74 75 reset-gpios: 76 description: Must contain a phandle to a GPIO controller followed by GPIO 77 that is being used as PERST input signal. Please refer to pci.txt. 78 79 phys: 80 minItems: 1 81 maxItems: 8 82 83 phy-names: 84 minItems: 1 85 items: 86 - const: p2u-0 87 - const: p2u-1 88 - const: p2u-2 89 - const: p2u-3 90 - const: p2u-4 91 - const: p2u-5 92 - const: p2u-6 93 - const: p2u-7 94 95 power-domains: 96 maxItems: 1 97 description: | 98 A phandle to the node that controls power to the respective PCIe 99 controller and a specifier name for the PCIe controller. 100 101 Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" 102 Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" 103 104 interconnects: 105 items: 106 - description: memory read client 107 - description: memory write client 108 109 interconnect-names: 110 items: 111 - const: dma-mem # read 112 - const: write 113 114 dma-coherent: true 115 116 nvidia,bpmp: 117 $ref: /schemas/types.yaml#/definitions/phandle-array 118 description: | 119 Must contain a pair of phandles to BPMP controller node followed by 120 controller ID. Following are the controller IDs for each controller: 121 122 Tegra194 123 124 0: C0 125 1: C1 126 2: C2 127 3: C3 128 4: C4 129 5: C5 130 131 Tegra234 132 133 0 : C0 134 1 : C1 135 2 : C2 136 3 : C3 137 4 : C4 138 5 : C5 139 6 : C6 140 7 : C7 141 8 : C8 142 9 : C9 143 10: C10 144 145 items: 146 - items: 147 - description: phandle to BPMP controller node 148 - description: PCIe controller ID 149 maximum: 10 150 151 nvidia,aspm-cmrt-us: 152 description: Common Mode Restore Time for proper operation of ASPM to be 153 specified in microseconds 154 155 nvidia,aspm-pwr-on-t-us: 156 description: Power On time for proper operation of ASPM to be specified in 157 microseconds 158 159 nvidia,aspm-l0s-entrance-latency-us: 160 description: ASPM L0s entrance latency to be specified in microseconds 161 162 vddio-pex-ctl-supply: 163 description: A phandle to the regulator supply for PCIe side band signals 164 165 nvidia,refclk-select-gpios: 166 maxItems: 1 167 description: GPIO used to enable REFCLK to controller from the host 168 169 nvidia,enable-ext-refclk: 170 description: | 171 This boolean property needs to be present if the controller is configured 172 to receive Reference Clock from the host. 173 NOTE: This is applicable only for Tegra234. 174 175 $ref: /schemas/types.yaml#/definitions/flag 176 177 nvidia,enable-srns: 178 description: | 179 This boolean property needs to be present if the controller is 180 configured to operate in SRNS (Separate Reference Clocks with No 181 Spread-Spectrum Clocking). NOTE: This is applicable only for 182 Tegra234. 183 184 $ref: /schemas/types.yaml#/definitions/flag 185 186allOf: 187 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 188 189unevaluatedProperties: false 190 191required: 192 - interrupts 193 - interrupt-names 194 - clocks 195 - clock-names 196 - resets 197 - reset-names 198 - power-domains 199 - reset-gpios 200 - vddio-pex-ctl-supply 201 - num-lanes 202 - phys 203 - phy-names 204 - nvidia,bpmp 205 206examples: 207 - | 208 #include <dt-bindings/clock/tegra194-clock.h> 209 #include <dt-bindings/gpio/tegra194-gpio.h> 210 #include <dt-bindings/interrupt-controller/arm-gic.h> 211 #include <dt-bindings/power/tegra194-powergate.h> 212 #include <dt-bindings/reset/tegra194-reset.h> 213 214 bus@0 { 215 #address-cells = <2>; 216 #size-cells = <2>; 217 ranges = <0x0 0x0 0x0 0x8 0x0>; 218 219 pcie-ep@141a0000 { 220 compatible = "nvidia,tegra194-pcie-ep"; 221 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 222 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 223 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 224 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 225 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 226 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 227 interrupt-names = "intr"; 228 229 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 230 clock-names = "core"; 231 232 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 233 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 234 reset-names = "apb", "core"; 235 236 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 239 240 nvidia,bpmp = <&bpmp 5>; 241 242 nvidia,aspm-cmrt-us = <60>; 243 nvidia,aspm-pwr-on-t-us = <20>; 244 nvidia,aspm-l0s-entrance-latency-us = <3>; 245 246 vddio-pex-ctl-supply = <&vdd_1v8ao>; 247 248 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 249 250 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 251 GPIO_ACTIVE_HIGH>; 252 253 num-lanes = <8>; 254 255 phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 256 <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 257 <&p2u_nvhs_6>, <&p2u_nvhs_7>; 258 259 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 260 "p2u-5", "p2u-6", "p2u-7"; 261 }; 262 }; 263 264 - | 265 #include <dt-bindings/clock/tegra234-clock.h> 266 #include <dt-bindings/gpio/tegra234-gpio.h> 267 #include <dt-bindings/interrupt-controller/arm-gic.h> 268 #include <dt-bindings/power/tegra234-powergate.h> 269 #include <dt-bindings/reset/tegra234-reset.h> 270 271 bus@0 { 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges = <0x0 0x0 0x0 0x8 0x0>; 275 276 pcie-ep@141a0000 { 277 compatible = "nvidia,tegra234-pcie-ep"; 278 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 279 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 280 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 281 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 282 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 283 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 284 285 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 286 interrupt-names = "intr"; 287 288 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 289 clock-names = "core"; 290 291 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 292 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 293 reset-names = "apb", "core"; 294 295 nvidia,bpmp = <&bpmp 5>; 296 297 nvidia,enable-ext-refclk; 298 nvidia,aspm-cmrt-us = <60>; 299 nvidia,aspm-pwr-on-t-us = <20>; 300 nvidia,aspm-l0s-entrance-latency-us = <3>; 301 302 vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>; 303 304 reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; 305 306 nvidia,refclk-select-gpios = <&gpio_aon 307 TEGRA234_AON_GPIO(AA, 4) 308 GPIO_ACTIVE_HIGH>; 309 310 num-lanes = <8>; 311 312 phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 313 <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 314 <&p2u_nvhs_6>, <&p2u_nvhs_7>; 315 316 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 317 "p2u-5", "p2u-6", "p2u-7"; 318 }; 319 }; 320