1* Marvell EBU PCIe interfaces 2 3Mandatory properties: 4 5- compatible: one of the following values: 6 marvell,armada-370-pcie 7 marvell,armada-xp-pcie 8 marvell,dove-pcie 9 marvell,kirkwood-pcie 10- #address-cells, set to <3> 11- #size-cells, set to <2> 12- #interrupt-cells, set to <1> 13- bus-range: PCI bus numbers covered 14- device_type, set to "pci" 15- ranges: ranges describing the MMIO registers to control the PCIe 16 interfaces, and ranges describing the MBus windows needed to access 17 the memory and I/O regions of each PCIe interface. 18- msi-parent: Link to the hardware entity that serves as the Message 19 Signaled Interrupt controller for this PCI controller. 20 21The ranges describing the MMIO registers have the following layout: 22 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 24 25where: 26 27 * r is a 32-bits value that gives the offset of the MMIO 28 registers of this PCIe interface, from the base of the internal 29 registers. 30 31 * s is a 32-bits value that give the size of this MMIO 32 registers area. This range entry translates the '0x82000000 0 r' PCI 33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part 34 of the internal register window (as identified by MBUS_ID(0xf0, 35 0x01)). 36 37The ranges describing the MBus windows have the following layout: 38 39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 40 41where: 42 43 * t is the type of the MBus window (as defined by the standard PCI DT 44 bindings), 1 for I/O and 2 for memory. 45 46 * s is the PCI slot that corresponds to this PCIe interface 47 48 * w is the 'target ID' value for the MBus window 49 50 * a the 'attribute' value for the MBus window. 51 52Since the location and size of the different MBus windows is not fixed in 53hardware, and only determined in runtime, those ranges cover the full first 544 GB of the physical address space, and do not translate into a valid CPU 55address. 56 57In addition, the device tree node must have sub-nodes describing each 58PCIe interface, having the following mandatory properties: 59 60- reg: used only for interrupt mapping, so only the first four bytes 61 are used to refer to the correct bus number and device number. 62- assigned-addresses: reference to the MMIO registers used to control 63 this PCIe interface. 64- clocks: the clock associated to this PCIe interface 65- marvell,pcie-port: the physical PCIe port number 66- status: either "disabled" or "okay" 67- device_type, set to "pci" 68- #address-cells, set to <3> 69- #size-cells, set to <2> 70- #interrupt-cells, set to <1> 71- ranges, translating the MBus windows ranges of the parent node into 72 standard PCI addresses. 73- interrupt-map-mask and interrupt-map, standard PCI properties to 74 define the mapping of the PCIe interface to interrupt numbers. 75 76and the following optional properties: 77- marvell,pcie-lane: the physical PCIe lane number, for ports having 78 multiple lanes. If this property is not found, we assume that the 79 value is 0. 80- num-lanes: number of SerDes PCIe lanes for this link (1 or 4) 81- reset-gpios: optional GPIO to PERST# 82- reset-delay-us: delay in us to wait after reset de-assertion, if not 83 specified will default to 100ms, as required by the PCIe specification. 84- interrupt-names: list of interrupt names, supported are: 85 - "intx" - interrupt line triggered by one of the legacy interrupt 86- interrupts or interrupts-extended: List of the interrupt sources which 87 corresponding to the "interrupt-names". If non-empty then also additional 88 'interrupt-controller' subnode must be defined. 89 90Example: 91 92pcie-controller { 93 compatible = "marvell,armada-xp-pcie"; 94 device_type = "pci"; 95 96 #address-cells = <3>; 97 #size-cells = <2>; 98 99 bus-range = <0x00 0xff>; 100 msi-parent = <&mpic>; 101 102 ranges = 103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 105 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 106 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 107 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 108 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 109 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 110 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 111 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 112 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 113 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 114 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 115 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 116 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 117 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 118 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 119 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 120 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 121 122 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 123 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 124 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 125 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 126 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 127 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 128 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 129 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 130 131 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 132 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 133 134 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 135 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 136 137 pcie@1,0 { 138 device_type = "pci"; 139 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 140 reg = <0x0800 0 0 0 0>; 141 #address-cells = <3>; 142 #size-cells = <2>; 143 #interrupt-cells = <1>; 144 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 145 0x81000000 0 0 0x81000000 0x1 0 1 0>; 146 interrupt-map-mask = <0 0 0 0>; 147 interrupt-map = <0 0 0 0 &mpic 58>; 148 marvell,pcie-port = <0>; 149 marvell,pcie-lane = <0>; 150 num-lanes = <1>; 151 /* low-active PERST# reset on GPIO 25 */ 152 reset-gpios = <&gpio0 25 1>; 153 /* wait 20ms for device settle after reset deassertion */ 154 reset-delay-us = <20000>; 155 clocks = <&gateclk 5>; 156 }; 157 158 pcie@2,0 { 159 device_type = "pci"; 160 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 161 reg = <0x1000 0 0 0 0>; 162 #address-cells = <3>; 163 #size-cells = <2>; 164 #interrupt-cells = <1>; 165 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 166 0x81000000 0 0 0x81000000 0x2 0 1 0>; 167 interrupt-map-mask = <0 0 0 0>; 168 interrupt-map = <0 0 0 0 &mpic 59>; 169 marvell,pcie-port = <0>; 170 marvell,pcie-lane = <1>; 171 num-lanes = <1>; 172 clocks = <&gateclk 6>; 173 }; 174 175 pcie@3,0 { 176 device_type = "pci"; 177 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 178 reg = <0x1800 0 0 0 0>; 179 #address-cells = <3>; 180 #size-cells = <2>; 181 #interrupt-cells = <1>; 182 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 183 0x81000000 0 0 0x81000000 0x3 0 1 0>; 184 interrupt-map-mask = <0 0 0 0>; 185 interrupt-map = <0 0 0 0 &mpic 60>; 186 marvell,pcie-port = <0>; 187 marvell,pcie-lane = <2>; 188 num-lanes = <1>; 189 clocks = <&gateclk 7>; 190 }; 191 192 pcie@4,0 { 193 device_type = "pci"; 194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 195 reg = <0x2000 0 0 0 0>; 196 #address-cells = <3>; 197 #size-cells = <2>; 198 #interrupt-cells = <1>; 199 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 200 0x81000000 0 0 0x81000000 0x4 0 1 0>; 201 interrupt-map-mask = <0 0 0 0>; 202 interrupt-map = <0 0 0 0 &mpic 61>; 203 marvell,pcie-port = <0>; 204 marvell,pcie-lane = <3>; 205 num-lanes = <1>; 206 clocks = <&gateclk 8>; 207 }; 208 209 pcie@5,0 { 210 device_type = "pci"; 211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 212 reg = <0x2800 0 0 0 0>; 213 #address-cells = <3>; 214 #size-cells = <2>; 215 #interrupt-cells = <1>; 216 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 217 0x81000000 0 0 0x81000000 0x5 0 1 0>; 218 interrupt-map-mask = <0 0 0 0>; 219 interrupt-map = <0 0 0 0 &mpic 62>; 220 marvell,pcie-port = <1>; 221 marvell,pcie-lane = <0>; 222 num-lanes = <1>; 223 clocks = <&gateclk 9>; 224 }; 225 226 pcie@6,0 { 227 device_type = "pci"; 228 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 229 reg = <0x3000 0 0 0 0>; 230 #address-cells = <3>; 231 #size-cells = <2>; 232 #interrupt-cells = <1>; 233 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 234 0x81000000 0 0 0x81000000 0x6 0 1 0>; 235 interrupt-map-mask = <0 0 0 0>; 236 interrupt-map = <0 0 0 0 &mpic 63>; 237 marvell,pcie-port = <1>; 238 marvell,pcie-lane = <1>; 239 num-lanes = <1>; 240 clocks = <&gateclk 10>; 241 }; 242 243 pcie@7,0 { 244 device_type = "pci"; 245 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 246 reg = <0x3800 0 0 0 0>; 247 #address-cells = <3>; 248 #size-cells = <2>; 249 #interrupt-cells = <1>; 250 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 251 0x81000000 0 0 0x81000000 0x7 0 1 0>; 252 interrupt-map-mask = <0 0 0 0>; 253 interrupt-map = <0 0 0 0 &mpic 64>; 254 marvell,pcie-port = <1>; 255 marvell,pcie-lane = <2>; 256 num-lanes = <1>; 257 clocks = <&gateclk 11>; 258 }; 259 260 pcie@8,0 { 261 device_type = "pci"; 262 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 263 reg = <0x4000 0 0 0 0>; 264 #address-cells = <3>; 265 #size-cells = <2>; 266 #interrupt-cells = <1>; 267 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 268 0x81000000 0 0 0x81000000 0x8 0 1 0>; 269 interrupt-map-mask = <0 0 0 0>; 270 interrupt-map = <0 0 0 0 &mpic 65>; 271 marvell,pcie-port = <1>; 272 marvell,pcie-lane = <3>; 273 num-lanes = <1>; 274 clocks = <&gateclk 12>; 275 }; 276 277 pcie@9,0 { 278 device_type = "pci"; 279 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 280 reg = <0x4800 0 0 0 0>; 281 #address-cells = <3>; 282 #size-cells = <2>; 283 #interrupt-cells = <1>; 284 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 285 0x81000000 0 0 0x81000000 0x9 0 1 0>; 286 interrupt-map-mask = <0 0 0 0>; 287 interrupt-map = <0 0 0 0 &mpic 99>; 288 marvell,pcie-port = <2>; 289 marvell,pcie-lane = <0>; 290 num-lanes = <1>; 291 clocks = <&gateclk 26>; 292 }; 293 294 pcie@a,0 { 295 device_type = "pci"; 296 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 297 reg = <0x5000 0 0 0 0>; 298 #address-cells = <3>; 299 #size-cells = <2>; 300 #interrupt-cells = <1>; 301 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 302 0x81000000 0 0 0x81000000 0xa 0 1 0>; 303 interrupt-map-mask = <0 0 0 0>; 304 interrupt-map = <0 0 0 0 &mpic 103>; 305 marvell,pcie-port = <3>; 306 marvell,pcie-lane = <0>; 307 num-lanes = <1>; 308 clocks = <&gateclk 27>; 309 }; 310}; 311