1MediaTek Gen2 PCIe controller 2 3Required properties: 4- compatible: Should contain one of the following strings: 5 "mediatek,mt2701-pcie" 6 "mediatek,mt2712-pcie" 7 "mediatek,mt7622-pcie" 8 "mediatek,mt7623-pcie" 9 "mediatek,mt7629-pcie" 10- device_type: Must be "pci" 11- reg: Base addresses and lengths of the root ports. 12- reg-names: Names of the above areas to use during resource lookup. 13- #address-cells: Address representation for root ports (must be 3) 14- #size-cells: Size representation for root ports (must be 2) 15- clocks: Must contain an entry for each entry in clock-names. 16 See ../clocks/clock-bindings.txt for details. 17- clock-names: 18 Mandatory entries: 19 - sys_ckN :transaction layer and data link layer clock 20 Required entries for MT2701/MT7623: 21 - free_ck :for reference clock of PCIe subsys 22 Required entries for MT2712/MT7622: 23 - ahb_ckN :AHB slave interface operating clock for CSR access and RC 24 initiated MMIO access 25 Required entries for MT7622: 26 - axi_ckN :application layer MMIO channel operating clock 27 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when 28 pcie_mac_ck/pcie_pipe_ck is turned off 29 - obff_ckN :OBFF functional block operating clock 30 - pipe_ckN :LTSSM and PHY/MAC layer operating clock 31 where N starting from 0 to one less than the number of root ports. 32- phys: List of PHY specifiers (used by generic PHY framework). 33- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the 34 number of PHYs as specified in *phys* property. 35- power-domains: A phandle and power domain specifier pair to the power domain 36 which is responsible for collapsing and restoring power to the peripheral. 37- bus-range: Range of bus numbers associated with this controller. 38- ranges: Ranges for the PCI memory and I/O regions. 39 40Required properties for MT7623/MT2701: 41- #interrupt-cells: Size representation for interrupts (must be 1) 42- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 43 Please refer to the standard PCI bus binding document for a more detailed 44 explanation. 45- resets: Must contain an entry for each entry in reset-names. 46 See ../reset/reset.txt for details. 47- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the 48 number of root ports. 49 50Required properties for MT2712/MT7622/MT7629: 51-interrupts: A list of interrupt outputs of the controller, must have one 52 entry for each PCIe port 53- interrupt-names: Must include the following entries: 54 - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received 55- linux,pci-domain: PCI domain ID. Should be unique for each host controller 56 57In addition, the device tree node must have sub-nodes describing each 58PCIe port interface, having the following mandatory properties: 59 60Required properties: 61- device_type: Must be "pci" 62- reg: Only the first four bytes are used to refer to the correct bus number 63 and device number. 64- #address-cells: Must be 3 65- #size-cells: Must be 2 66- #interrupt-cells: Must be 1 67- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 68 Please refer to the standard PCI bus binding document for a more detailed 69 explanation. 70- ranges: Sub-ranges distributed from the PCIe controller node. An empty 71 property is sufficient. 72 73Examples for MT7623: 74 75 hifsys: syscon@1a000000 { 76 compatible = "mediatek,mt7623-hifsys", 77 "mediatek,mt2701-hifsys", 78 "syscon"; 79 reg = <0 0x1a000000 0 0x1000>; 80 #clock-cells = <1>; 81 #reset-cells = <1>; 82 }; 83 84 pcie: pcie@1a140000 { 85 compatible = "mediatek,mt7623-pcie"; 86 device_type = "pci"; 87 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ 88 <0 0x1a142000 0 0x1000>, /* Port0 registers */ 89 <0 0x1a143000 0 0x1000>, /* Port1 registers */ 90 <0 0x1a144000 0 0x1000>; /* Port2 registers */ 91 reg-names = "subsys", "port0", "port1", "port2"; 92 #address-cells = <3>; 93 #size-cells = <2>; 94 #interrupt-cells = <1>; 95 interrupt-map-mask = <0xf800 0 0 0>; 96 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, 97 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, 98 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 99 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 100 <&hifsys CLK_HIFSYS_PCIE0>, 101 <&hifsys CLK_HIFSYS_PCIE1>, 102 <&hifsys CLK_HIFSYS_PCIE2>; 103 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; 104 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, 105 <&hifsys MT2701_HIFSYS_PCIE1_RST>, 106 <&hifsys MT2701_HIFSYS_PCIE2_RST>; 107 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; 108 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, 109 <&pcie2_phy PHY_TYPE_PCIE>; 110 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; 111 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 112 bus-range = <0x00 0xff>; 113 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ 114 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ 115 116 pcie@0,0 { 117 reg = <0x0000 0 0 0 0>; 118 #address-cells = <3>; 119 #size-cells = <2>; 120 #interrupt-cells = <1>; 121 interrupt-map-mask = <0 0 0 0>; 122 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 123 ranges; 124 }; 125 126 pcie@1,0 { 127 reg = <0x0800 0 0 0 0>; 128 #address-cells = <3>; 129 #size-cells = <2>; 130 #interrupt-cells = <1>; 131 interrupt-map-mask = <0 0 0 0>; 132 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 133 ranges; 134 }; 135 136 pcie@2,0 { 137 reg = <0x1000 0 0 0 0>; 138 #address-cells = <3>; 139 #size-cells = <2>; 140 #interrupt-cells = <1>; 141 interrupt-map-mask = <0 0 0 0>; 142 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 143 ranges; 144 }; 145 }; 146 147Examples for MT2712: 148 149 pcie1: pcie@112ff000 { 150 compatible = "mediatek,mt2712-pcie"; 151 device_type = "pci"; 152 reg = <0 0x112ff000 0 0x1000>; 153 reg-names = "port1"; 154 linux,pci-domain = <1>; 155 #address-cells = <3>; 156 #size-cells = <2>; 157 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "pcie_irq"; 159 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 160 <&pericfg CLK_PERI_PCIE1>; 161 clock-names = "sys_ck1", "ahb_ck1"; 162 phys = <&u3port1 PHY_TYPE_PCIE>; 163 phy-names = "pcie-phy1"; 164 bus-range = <0x00 0xff>; 165 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; 166 status = "disabled"; 167 168 #interrupt-cells = <1>; 169 interrupt-map-mask = <0 0 0 7>; 170 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 171 <0 0 0 2 &pcie_intc1 1>, 172 <0 0 0 3 &pcie_intc1 2>, 173 <0 0 0 4 &pcie_intc1 3>; 174 pcie_intc1: interrupt-controller { 175 interrupt-controller; 176 #address-cells = <0>; 177 #interrupt-cells = <1>; 178 }; 179 }; 180 181 pcie0: pcie@11700000 { 182 compatible = "mediatek,mt2712-pcie"; 183 device_type = "pci"; 184 reg = <0 0x11700000 0 0x1000>; 185 reg-names = "port0"; 186 linux,pci-domain = <0>; 187 #address-cells = <3>; 188 #size-cells = <2>; 189 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 190 interrupt-names = "pcie_irq"; 191 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 192 <&pericfg CLK_PERI_PCIE0>; 193 clock-names = "sys_ck0", "ahb_ck0"; 194 phys = <&u3port0 PHY_TYPE_PCIE>; 195 phy-names = "pcie-phy0"; 196 bus-range = <0x00 0xff>; 197 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 198 status = "disabled"; 199 200 #interrupt-cells = <1>; 201 interrupt-map-mask = <0 0 0 7>; 202 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 203 <0 0 0 2 &pcie_intc0 1>, 204 <0 0 0 3 &pcie_intc0 2>, 205 <0 0 0 4 &pcie_intc0 3>; 206 pcie_intc0: interrupt-controller { 207 interrupt-controller; 208 #address-cells = <0>; 209 #interrupt-cells = <1>; 210 }; 211 }; 212 213Examples for MT7622: 214 215 pcie0: pcie@1a143000 { 216 compatible = "mediatek,mt7622-pcie"; 217 device_type = "pci"; 218 reg = <0 0x1a143000 0 0x1000>; 219 reg-names = "port0"; 220 linux,pci-domain = <0>; 221 #address-cells = <3>; 222 #size-cells = <2>; 223 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 224 interrupt-names = "pcie_irq"; 225 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, 226 <&pciesys CLK_PCIE_P0_AHB_EN>, 227 <&pciesys CLK_PCIE_P0_AUX_EN>, 228 <&pciesys CLK_PCIE_P0_AXI_EN>, 229 <&pciesys CLK_PCIE_P0_OBFF_EN>, 230 <&pciesys CLK_PCIE_P0_PIPE_EN>; 231 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", 232 "axi_ck0", "obff_ck0", "pipe_ck0"; 233 234 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 235 bus-range = <0x00 0xff>; 236 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; 237 status = "disabled"; 238 239 #interrupt-cells = <1>; 240 interrupt-map-mask = <0 0 0 7>; 241 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 242 <0 0 0 2 &pcie_intc0 1>, 243 <0 0 0 3 &pcie_intc0 2>, 244 <0 0 0 4 &pcie_intc0 3>; 245 pcie_intc0: interrupt-controller { 246 interrupt-controller; 247 #address-cells = <0>; 248 #interrupt-cells = <1>; 249 }; 250 }; 251 252 pcie1: pcie@1a145000 { 253 compatible = "mediatek,mt7622-pcie"; 254 device_type = "pci"; 255 reg = <0 0x1a145000 0 0x1000>; 256 reg-names = "port1"; 257 linux,pci-domain = <1>; 258 #address-cells = <3>; 259 #size-cells = <2>; 260 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 261 interrupt-names = "pcie_irq"; 262 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, 263 /* designer has connect RC1 with p0_ahb clock */ 264 <&pciesys CLK_PCIE_P0_AHB_EN>, 265 <&pciesys CLK_PCIE_P1_AUX_EN>, 266 <&pciesys CLK_PCIE_P1_AXI_EN>, 267 <&pciesys CLK_PCIE_P1_OBFF_EN>, 268 <&pciesys CLK_PCIE_P1_PIPE_EN>; 269 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", 270 "axi_ck1", "obff_ck1", "pipe_ck1"; 271 272 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 273 bus-range = <0x00 0xff>; 274 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; 275 status = "disabled"; 276 277 #interrupt-cells = <1>; 278 interrupt-map-mask = <0 0 0 7>; 279 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 280 <0 0 0 2 &pcie_intc1 1>, 281 <0 0 0 3 &pcie_intc1 2>, 282 <0 0 0 4 &pcie_intc1 3>; 283 pcie_intc1: interrupt-controller { 284 interrupt-controller; 285 #address-cells = <0>; 286 #interrupt-cells = <1>; 287 }; 288 }; 289