xref: /freebsd/sys/contrib/device-tree/Bindings/pci/mediatek-pcie-gen3.yaml (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Gen3 PCIe controller on MediaTek SoCs
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |+
13  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14  and compatible with Gen2, Gen1 speed.
15
16  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17  block diagram is as follows:
18
19                    +-----+
20                    | GIC |
21                    +-----+
22                       ^
23                       |
24                   port->irq
25                       |
26               +-+-+-+-+-+-+-+-+
27               |0|1|2|3|4|5|6|7| (PCIe intc)
28               +-+-+-+-+-+-+-+-+
29                ^ ^           ^
30                | |    ...    |
31        +-------+ +------+    +-----------+
32        |                |                |
33  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
34  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
35  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
36   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
37   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
38   | |      |  |    | |      |  |    | |      |  |
39
40    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
41
42  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43  each set has its own address for MSI message, and supports 32 MSI vectors
44  to generate interrupt.
45
46allOf:
47  - $ref: /schemas/pci/pci-bus.yaml#
48
49properties:
50  compatible:
51    oneOf:
52      - items:
53          - enum:
54              - mediatek,mt8188-pcie
55              - mediatek,mt8195-pcie
56          - const: mediatek,mt8192-pcie
57      - const: mediatek,mt8192-pcie
58
59  reg:
60    maxItems: 1
61
62  reg-names:
63    items:
64      - const: pcie-mac
65
66  interrupts:
67    maxItems: 1
68
69  ranges:
70    minItems: 1
71    maxItems: 8
72
73  resets:
74    minItems: 1
75    maxItems: 2
76
77  reset-names:
78    minItems: 1
79    items:
80      - const: phy
81      - const: mac
82
83  clocks:
84    maxItems: 6
85
86  clock-names:
87    items:
88      - const: pl_250m
89      - const: tl_26m
90      - const: tl_96m
91      - const: tl_32k
92      - const: peri_26m
93      - enum:
94          - top_133m        # for MT8192
95          - peri_mem        # for MT8188/MT8195
96
97  assigned-clocks:
98    maxItems: 1
99
100  assigned-clock-parents:
101    maxItems: 1
102
103  phys:
104    maxItems: 1
105
106  phy-names:
107    items:
108      - const: pcie-phy
109
110  '#interrupt-cells':
111    const: 1
112
113  interrupt-controller:
114    description: Interrupt controller node for handling legacy PCI interrupts.
115    type: object
116    properties:
117      '#address-cells':
118        const: 0
119      '#interrupt-cells':
120        const: 1
121      interrupt-controller: true
122
123    required:
124      - '#address-cells'
125      - '#interrupt-cells'
126      - interrupt-controller
127
128    additionalProperties: false
129
130required:
131  - compatible
132  - reg
133  - reg-names
134  - interrupts
135  - ranges
136  - clocks
137  - clock-names
138  - '#interrupt-cells'
139  - interrupt-controller
140
141unevaluatedProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146    #include <dt-bindings/interrupt-controller/irq.h>
147
148    bus {
149        #address-cells = <2>;
150        #size-cells = <2>;
151
152        pcie: pcie@11230000 {
153            compatible = "mediatek,mt8192-pcie";
154            device_type = "pci";
155            #address-cells = <3>;
156            #size-cells = <2>;
157            reg = <0x00 0x11230000 0x00 0x4000>;
158            reg-names = "pcie-mac";
159            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
160            bus-range = <0x00 0xff>;
161            ranges = <0x82000000 0x00 0x12000000 0x00
162                      0x12000000 0x00 0x1000000>;
163            clocks = <&infracfg 44>,
164                     <&infracfg 40>,
165                     <&infracfg 43>,
166                     <&infracfg 97>,
167                     <&infracfg 99>,
168                     <&infracfg 111>;
169            clock-names = "pl_250m", "tl_26m", "tl_96m",
170                          "tl_32k", "peri_26m", "top_133m";
171            assigned-clocks = <&topckgen 50>;
172            assigned-clock-parents = <&topckgen 91>;
173
174            phys = <&pciephy>;
175            phy-names = "pcie-phy";
176
177            resets = <&infracfg_rst 2>,
178                     <&infracfg_rst 3>;
179            reset-names = "phy", "mac";
180
181            #interrupt-cells = <1>;
182            interrupt-map-mask = <0 0 0 0x7>;
183            interrupt-map = <0 0 0 1 &pcie_intc 0>,
184                            <0 0 0 2 &pcie_intc 1>,
185                            <0 0 0 3 &pcie_intc 2>,
186                            <0 0 0 4 &pcie_intc 3>;
187            pcie_intc: interrupt-controller {
188                      #address-cells = <0>;
189                      #interrupt-cells = <1>;
190                      interrupt-controller;
191            };
192        };
193    };
194