xref: /freebsd/sys/contrib/device-tree/Bindings/pci/mediatek-pcie-gen3.yaml (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Gen3 PCIe controller on MediaTek SoCs
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |+
13  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14  and compatible with Gen2, Gen1 speed.
15
16  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17  block diagram is as follows:
18
19                    +-----+
20                    | GIC |
21                    +-----+
22                       ^
23                       |
24                   port->irq
25                       |
26               +-+-+-+-+-+-+-+-+
27               |0|1|2|3|4|5|6|7| (PCIe intc)
28               +-+-+-+-+-+-+-+-+
29                ^ ^           ^
30                | |    ...    |
31        +-------+ +------+    +-----------+
32        |                |                |
33  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
34  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
35  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
36   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
37   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
38   | |      |  |    | |      |  |    | |      |  |
39
40    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
41
42  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43  each set has its own address for MSI message, and supports 32 MSI vectors
44  to generate interrupt.
45
46allOf:
47  - $ref: /schemas/pci/pci-bus.yaml#
48
49properties:
50  compatible:
51    const: mediatek,mt8192-pcie
52
53  reg:
54    maxItems: 1
55
56  reg-names:
57    items:
58      - const: pcie-mac
59
60  interrupts:
61    maxItems: 1
62
63  ranges:
64    minItems: 1
65    maxItems: 8
66
67  resets:
68    minItems: 1
69    maxItems: 2
70
71  reset-names:
72    minItems: 1
73    items:
74      - const: phy
75      - const: mac
76
77  clocks:
78    maxItems: 6
79
80  clock-names:
81    items:
82      - const: pl_250m
83      - const: tl_26m
84      - const: tl_96m
85      - const: tl_32k
86      - const: peri_26m
87      - const: top_133m
88
89  assigned-clocks:
90    maxItems: 1
91
92  assigned-clock-parents:
93    maxItems: 1
94
95  phys:
96    maxItems: 1
97
98  '#interrupt-cells':
99    const: 1
100
101  interrupt-controller:
102    description: Interrupt controller node for handling legacy PCI interrupts.
103    type: object
104    properties:
105      '#address-cells':
106        const: 0
107      '#interrupt-cells':
108        const: 1
109      interrupt-controller: true
110
111    required:
112      - '#address-cells'
113      - '#interrupt-cells'
114      - interrupt-controller
115
116    additionalProperties: false
117
118required:
119  - compatible
120  - reg
121  - reg-names
122  - interrupts
123  - ranges
124  - clocks
125  - '#interrupt-cells'
126  - interrupt-controller
127
128unevaluatedProperties: false
129
130examples:
131  - |
132    #include <dt-bindings/interrupt-controller/arm-gic.h>
133    #include <dt-bindings/interrupt-controller/irq.h>
134
135    bus {
136        #address-cells = <2>;
137        #size-cells = <2>;
138
139        pcie: pcie@11230000 {
140            compatible = "mediatek,mt8192-pcie";
141            device_type = "pci";
142            #address-cells = <3>;
143            #size-cells = <2>;
144            reg = <0x00 0x11230000 0x00 0x4000>;
145            reg-names = "pcie-mac";
146            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
147            bus-range = <0x00 0xff>;
148            ranges = <0x82000000 0x00 0x12000000 0x00
149                      0x12000000 0x00 0x1000000>;
150            clocks = <&infracfg 44>,
151                     <&infracfg 40>,
152                     <&infracfg 43>,
153                     <&infracfg 97>,
154                     <&infracfg 99>,
155                     <&infracfg 111>;
156            clock-names = "pl_250m", "tl_26m", "tl_96m",
157                          "tl_32k", "peri_26m", "top_133m";
158            assigned-clocks = <&topckgen 50>;
159            assigned-clock-parents = <&topckgen 91>;
160
161            phys = <&pciephy>;
162            phy-names = "pcie-phy";
163
164            resets = <&infracfg_rst 2>,
165                     <&infracfg_rst 3>;
166            reset-names = "phy", "mac";
167
168            #interrupt-cells = <1>;
169            interrupt-map-mask = <0 0 0 0x7>;
170            interrupt-map = <0 0 0 1 &pcie_intc 0>,
171                            <0 0 0 2 &pcie_intc 1>,
172                            <0 0 0 3 &pcie_intc 2>,
173                            <0 0 0 4 &pcie_intc 3>;
174            pcie_intc: interrupt-controller {
175                      #address-cells = <0>;
176                      #interrupt-cells = <1>;
177                      interrupt-controller;
178            };
179        };
180    };
181