xref: /freebsd/sys/contrib/device-tree/Bindings/pci/mediatek,mt7621-pcie.yaml (revision 8cc087a1eee9ec1ca9f7ac1e63ad51bdb5a682eb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek MT7621 PCIe controller
8
9maintainers:
10  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11
12description: |+
13  MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14  with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
15
16allOf:
17  - $ref: /schemas/pci/pci-bus.yaml#
18
19properties:
20  compatible:
21    const: mediatek,mt7621-pci
22
23  reg:
24    items:
25      - description: host-pci bridge registers
26      - description: pcie port 0 RC control registers
27      - description: pcie port 1 RC control registers
28      - description: pcie port 2 RC control registers
29
30  ranges:
31    maxItems: 2
32
33patternProperties:
34  'pcie@[0-2],0':
35    type: object
36    $ref: /schemas/pci/pci-bus.yaml#
37
38    properties:
39      resets:
40        maxItems: 1
41
42      clocks:
43        maxItems: 1
44
45      phys:
46        maxItems: 1
47
48    required:
49      - "#interrupt-cells"
50      - interrupt-map-mask
51      - interrupt-map
52      - resets
53      - clocks
54      - phys
55      - phy-names
56      - ranges
57
58    unevaluatedProperties: false
59
60required:
61  - compatible
62  - reg
63  - ranges
64  - "#interrupt-cells"
65  - interrupt-map-mask
66  - interrupt-map
67  - reset-gpios
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/gpio/gpio.h>
74    #include <dt-bindings/interrupt-controller/mips-gic.h>
75
76    pcie: pcie@1e140000 {
77        compatible = "mediatek,mt7621-pci";
78        reg = <0x1e140000 0x100>,
79              <0x1e142000 0x100>,
80              <0x1e143000 0x100>,
81              <0x1e144000 0x100>;
82
83        #address-cells = <3>;
84        #size-cells = <2>;
85        pinctrl-names = "default";
86        pinctrl-0 = <&pcie_pins>;
87        device_type = "pci";
88        ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */
89                 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */
90        #interrupt-cells = <1>;
91        interrupt-map-mask = <0xF800 0 0 0>;
92        interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
93                        <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
94                        <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
95        reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
96
97        pcie@0,0 {
98            reg = <0x0000 0 0 0 0>;
99            #address-cells = <3>;
100            #size-cells = <2>;
101            device_type = "pci";
102            #interrupt-cells = <1>;
103            interrupt-map-mask = <0 0 0 0>;
104            interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
105            resets = <&rstctrl 24>;
106            clocks = <&clkctrl 24>;
107            phys = <&pcie0_phy 1>;
108            phy-names = "pcie-phy0";
109            ranges;
110        };
111
112        pcie@1,0 {
113            reg = <0x0800 0 0 0 0>;
114            #address-cells = <3>;
115            #size-cells = <2>;
116            device_type = "pci";
117            #interrupt-cells = <1>;
118            interrupt-map-mask = <0 0 0 0>;
119            interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
120            resets = <&rstctrl 25>;
121            clocks = <&clkctrl 25>;
122            phys = <&pcie0_phy 1>;
123            phy-names = "pcie-phy1";
124            ranges;
125        };
126
127        pcie@2,0 {
128            reg = <0x1000 0 0 0 0>;
129            #address-cells = <3>;
130            #size-cells = <2>;
131            device_type = "pci";
132            #interrupt-cells = <1>;
133            interrupt-map-mask = <0 0 0 0>;
134            interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
135            resets = <&rstctrl 26>;
136            clocks = <&clkctrl 26>;
137            phys = <&pcie2_phy 0>;
138            phy-names = "pcie-phy2";
139            ranges;
140        };
141    };
142...
143