1NXP Layerscape PCIe Gen4 controller 2 3This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all 4the common properties defined in mobiveil-pcie.txt. 5 6Required properties: 7- compatible: should contain the platform identifier such as: 8 "fsl,lx2160a-pcie" 9- reg: base addresses and lengths of the PCIe controller register blocks. 10 "csr_axi_slave": Bridge config registers 11 "config_axi_slave": PCIe controller registers 12- interrupts: A list of interrupt outputs of the controller. Must contain an 13 entry for each entry in the interrupt-names property. 14- interrupt-names: It could include the following entries: 15 "intr": The interrupt that is asserted for controller interrupts 16 "aer": Asserted for aer interrupt when chip support the aer interrupt with 17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer. 18 "pme": Asserted for pme interrupt when chip support the pme interrupt with 19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme. 20- dma-coherent: Indicates that the hardware IP block can ensure the coherency 21 of the data transferred from/to the IP block. This can avoid the software 22 cache flush/invalid actions, and improve the performance significantly. 23- msi-parent : See the generic MSI binding described in 24 Documentation/devicetree/bindings/interrupt-controller/msi.txt. 25 26Example: 27 28 pcie@3400000 { 29 compatible = "fsl,lx2160a-pcie"; 30 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 31 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 32 reg-names = "csr_axi_slave", "config_axi_slave"; 33 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 34 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 35 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 36 interrupt-names = "aer", "pme", "intr"; 37 #address-cells = <3>; 38 #size-cells = <2>; 39 device_type = "pci"; 40 apio-wins = <8>; 41 ppio-wins = <8>; 42 dma-coherent; 43 bus-range = <0x0 0xff>; 44 msi-parent = <&its>; 45 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; 46 #interrupt-cells = <1>; 47 interrupt-map-mask = <0 0 0 7>; 48 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 49 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 50 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 51 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 52 }; 53