1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Intel Keem Bay PCIe controller Endpoint mode 8 9maintainers: 10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> 11 - Srikanth Thokala <srikanth.thokala@intel.com> 12 13properties: 14 compatible: 15 const: intel,keembay-pcie-ep 16 17 reg: 18 maxItems: 5 19 20 reg-names: 21 items: 22 - const: dbi 23 - const: dbi2 24 - const: atu 25 - const: addr_space 26 - const: apb 27 28 interrupts: 29 maxItems: 4 30 31 interrupt-names: 32 items: 33 - const: pcie 34 - const: pcie_ev 35 - const: pcie_err 36 - const: pcie_mem_access 37 38 num-lanes: 39 description: Number of lanes to use. 40 enum: [ 1, 2 ] 41 42required: 43 - compatible 44 - reg 45 - reg-names 46 - interrupts 47 - interrupt-names 48 49additionalProperties: false 50 51examples: 52 - | 53 #include <dt-bindings/interrupt-controller/arm-gic.h> 54 #include <dt-bindings/interrupt-controller/irq.h> 55 pcie-ep@37000000 { 56 compatible = "intel,keembay-pcie-ep"; 57 reg = <0x37000000 0x00001000>, 58 <0x37100000 0x00001000>, 59 <0x37300000 0x00001000>, 60 <0x36000000 0x01000000>, 61 <0x37800000 0x00000200>; 62 reg-names = "dbi", "dbi2", "atu", "addr_space", "apb"; 63 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>, 65 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access"; 68 num-lanes = <2>; 69 }; 70