1HiSilicon Hip05 and Hip06 PCIe host bridge DT description 2 3HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. 4It shares common functions with the PCIe DesignWare core driver and inherits 5common properties defined in 6Documentation/devicetree/bindings/pci/designware-pcie.txt. 7 8Additional properties are described here: 9 10Required properties 11- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". 12- reg: Should contain rc_dbi, config registers location and length. 13- reg-names: Must include the following entries: 14 "rc_dbi": controller configuration registers; 15 "config": PCIe configuration space registers. 16- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. 17- port-id: Should be 0, 1, 2 or 3. 18 19Optional properties: 20- status: Either "ok" or "disabled". 21- dma-coherent: Present if DMA operations are coherent. 22 23Hip05 Example (note that Hip06 is the same except compatible): 24 pcie@b0080000 { 25 compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; 26 reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>; 27 reg-names = "rc_dbi", "config"; 28 bus-range = <0 15>; 29 msi-parent = <&its_pcie>; 30 #address-cells = <3>; 31 #size-cells = <2>; 32 device_type = "pci"; 33 dma-coherent; 34 ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>; 35 num-lanes = <8>; 36 port-id = <1>; 37 #interrupt-cells = <1>; 38 interrupt-map-mask = <0xf800 0 0 7>; 39 interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10 40 0x0 0 0 2 &mbigen_pcie 2 11 41 0x0 0 0 3 &mbigen_pcie 3 12 42 0x0 0 0 4 &mbigen_pcie 4 13>; 43 }; 44