xref: /freebsd/sys/contrib/device-tree/Bindings/pci/fsl,imx6q-pcie.yaml (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16  The controller instances are dual mode where in they can work either in
17  Root Port mode or Endpoint mode but one at a time.
18
19  See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
20  bindings.
21
22properties:
23  compatible:
24    enum:
25      - fsl,imx6q-pcie
26      - fsl,imx6sx-pcie
27      - fsl,imx6qp-pcie
28      - fsl,imx7d-pcie
29      - fsl,imx8mq-pcie
30      - fsl,imx8mm-pcie
31      - fsl,imx8mp-pcie
32
33  reg:
34    items:
35      - description: Data Bus Interface (DBI) registers.
36      - description: PCIe configuration space region.
37
38  reg-names:
39    items:
40      - const: dbi
41      - const: config
42
43  clocks:
44    minItems: 3
45    items:
46      - description: PCIe bridge clock.
47      - description: PCIe bus clock.
48      - description: PCIe PHY clock.
49      - description: Additional required clock entry for imx6sx-pcie,
50           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
51
52  clock-names:
53    minItems: 3
54    maxItems: 4
55
56  interrupts:
57    items:
58      - description: builtin MSI controller.
59
60  interrupt-names:
61    items:
62      - const: msi
63
64  reset-gpio:
65    description: Should specify the GPIO for controlling the PCI bus device
66      reset signal. It's not polarity aware and defaults to active-low reset
67      sequence (L=reset state, H=operation state) (optional required).
68
69  reset-gpio-active-high:
70    description: If present then the reset sequence using the GPIO
71      specified in the "reset-gpio" property is reversed (H=reset state,
72      L=operation state) (optional required).
73    type: boolean
74
75required:
76  - compatible
77  - reg
78  - reg-names
79  - "#address-cells"
80  - "#size-cells"
81  - device_type
82  - bus-range
83  - ranges
84  - interrupts
85  - interrupt-names
86  - "#interrupt-cells"
87  - interrupt-map-mask
88  - interrupt-map
89
90allOf:
91  - $ref: /schemas/pci/snps,dw-pcie.yaml#
92  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
93  - if:
94      properties:
95        compatible:
96          enum:
97            - fsl,imx6sx-pcie
98    then:
99      properties:
100        clocks:
101          minItems: 4
102        clock-names:
103          items:
104            - const: pcie
105            - const: pcie_bus
106            - const: pcie_phy
107            - const: pcie_inbound_axi
108
109  - if:
110      properties:
111        compatible:
112          enum:
113            - fsl,imx8mq-pcie
114    then:
115      properties:
116        clocks:
117          minItems: 4
118        clock-names:
119          items:
120            - const: pcie
121            - const: pcie_bus
122            - const: pcie_phy
123            - const: pcie_aux
124
125  - if:
126      properties:
127        compatible:
128          enum:
129            - fsl,imx6q-pcie
130            - fsl,imx6qp-pcie
131            - fsl,imx7d-pcie
132    then:
133      properties:
134        clocks:
135          maxItems: 3
136        clock-names:
137          items:
138            - const: pcie
139            - const: pcie_bus
140            - const: pcie_phy
141
142  - if:
143      properties:
144        compatible:
145          enum:
146            - fsl,imx8mm-pcie
147            - fsl,imx8mp-pcie
148    then:
149      properties:
150        clocks:
151          maxItems: 3
152        clock-names:
153          items:
154            - const: pcie
155            - const: pcie_bus
156            - const: pcie_aux
157
158unevaluatedProperties: false
159
160examples:
161  - |
162    #include <dt-bindings/clock/imx6qdl-clock.h>
163    #include <dt-bindings/interrupt-controller/arm-gic.h>
164
165    pcie: pcie@1ffc000 {
166        compatible = "fsl,imx6q-pcie";
167        reg = <0x01ffc000 0x04000>,
168              <0x01f00000 0x80000>;
169        reg-names = "dbi", "config";
170        #address-cells = <3>;
171        #size-cells = <2>;
172        device_type = "pci";
173        bus-range = <0x00 0xff>;
174        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
175                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
176        num-lanes = <1>;
177        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
178        interrupt-names = "msi";
179        #interrupt-cells = <1>;
180        interrupt-map-mask = <0 0 0 0x7>;
181        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
183                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
184                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
185        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
186                <&clks IMX6QDL_CLK_LVDS1_GATE>,
187                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
188        clock-names = "pcie", "pcie_bus", "pcie_phy";
189    };
190...
191