1* Synopsys DesignWare PCIe interface 2 3Required properties: 4- compatible: 5 "snps,dw-pcie" for RC mode; 6 "snps,dw-pcie-ep" for EP mode; 7- reg: For designware cores version < 4.80 contains the configuration 8 address space. For designware core version >= 4.80, contains 9 the configuration and ATU address space 10- reg-names: Must be "config" for the PCIe configuration space and "atu" for 11 the ATU address space. 12 (The old way of getting the configuration address space from "ranges" 13 is deprecated and should be avoided.) 14RC mode: 15- #address-cells: set to <3> 16- #size-cells: set to <2> 17- device_type: set to "pci" 18- ranges: ranges for the PCI memory and I/O regions 19- #interrupt-cells: set to <1> 20- interrupt-map-mask and interrupt-map: standard PCI 21 properties to define the mapping of the PCIe interface to interrupt 22 numbers. 23EP mode: 24- num-ib-windows: number of inbound address translation windows 25- num-ob-windows: number of outbound address translation windows 26 27Optional properties: 28- num-lanes: number of lanes to use (this property should be specified unless 29 the link is brought already up in BIOS) 30- reset-gpio: GPIO pin number of power good signal 31- clocks: Must contain an entry for each entry in clock-names. 32 See ../clocks/clock-bindings.txt for details. 33- clock-names: Must include the following entries: 34 - "pcie" 35 - "pcie_bus" 36- snps,enable-cdm-check: This is a boolean property and if present enables 37 automatic checking of CDM (Configuration Dependent Module) registers 38 for data corruption. CDM registers include standard PCIe configuration 39 space registers, Port Logic registers, DMA and iATU (internal Address 40 Translation Unit) registers. 41RC mode: 42- num-viewport: number of view ports configured in hardware. If a platform 43 does not specify it, the driver assumes 2. 44- bus-range: PCI bus numbers covered (it is recommended for new devicetrees 45 to specify this property, to keep backwards compatibility a range of 46 0x00-0xff is assumed if not present) 47 48EP mode: 49- max-functions: maximum number of functions that can be configured 50 51Example configuration: 52 53 pcie: pcie@dfc00000 { 54 compatible = "snps,dw-pcie"; 55 reg = <0xdfc00000 0x0001000>, /* IP registers */ 56 <0xd0000000 0x0002000>; /* Configuration space */ 57 reg-names = "dbi", "config"; 58 #address-cells = <3>; 59 #size-cells = <2>; 60 device_type = "pci"; 61 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 62 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; 63 interrupts = <25>, <24>; 64 #interrupt-cells = <1>; 65 num-lanes = <1>; 66 }; 67or 68 pcie: pcie@dfc00000 { 69 compatible = "snps,dw-pcie-ep"; 70 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ 71 <0xdfc01000 0x0001000>, /* IP registers 2 */ 72 <0xd0000000 0x2000000>; /* Configuration space */ 73 reg-names = "dbi", "dbi2", "addr_space"; 74 num-ib-windows = <6>; 75 num-ob-windows = <2>; 76 num-lanes = <1>; 77 }; 78