1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Brcmstb PCIe Host Controller 8 9maintainers: 10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - brcm,bcm2711-pcie # The Raspberry Pi 4 17 - brcm,bcm4908-pcie 18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4 19 - brcm,bcm7278-pcie # Broadcom 7278 Arm 20 - brcm,bcm7216-pcie # Broadcom 7216 Arm 21 - brcm,bcm7445-pcie # Broadcom 7445 Arm 22 - brcm,bcm7425-pcie # Broadcom 7425 MIPs 23 - brcm,bcm7435-pcie # Broadcom 7435 MIPs 24 25 reg: 26 maxItems: 1 27 28 interrupts: 29 minItems: 1 30 items: 31 - description: PCIe host controller 32 - description: builtin MSI controller 33 34 interrupt-names: 35 minItems: 1 36 items: 37 - const: pcie 38 - const: msi 39 40 ranges: 41 minItems: 1 42 maxItems: 4 43 44 dma-ranges: 45 minItems: 1 46 maxItems: 6 47 48 clocks: 49 maxItems: 1 50 51 clock-names: 52 items: 53 - const: sw_pcie 54 55 msi-controller: 56 description: Identifies the node as an MSI controller. 57 58 msi-parent: 59 description: MSI controller the device is capable of using. 60 61 brcm,enable-ssc: 62 description: Indicates usage of spread-spectrum clocking. 63 type: boolean 64 65 aspm-no-l0s: true 66 67 brcm,clkreq-mode: 68 description: A string that determines the operating 69 clkreq mode of the PCIe RC HW with respect to controlling the refclk 70 signal. There are three different modes -- "safe", which drives the 71 refclk signal unconditionally and will work for all devices but does 72 not provide any power savings; "no-l1ss" -- which provides Clock 73 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) 74 power savings. If the downstream device connected to the RC is L1SS 75 capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, 76 potentially hanging the system; "default" -- which provides L0s, L1, 77 and L1SS, but not compliant to provide Clock Power Management; 78 specifically, may not be able to meet the T_CLRon max timing of 400ns 79 as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI 80 Express Mini CEM 2.1 specification. This situation is atypical and 81 should happen only with older devices. 82 $ref: /schemas/types.yaml#/definitions/string 83 enum: [ safe, no-l1ss, default ] 84 85 brcm,scb-sizes: 86 description: u64 giving the 64bit PCIe memory 87 viewport size of a memory controller. There may be up to 88 three controllers, and each size must be a power of two 89 with a size greater or equal to the amount of memory the 90 controller supports. Note that each memory controller 91 may have two component regions -- base and extended -- so 92 this information cannot be deduced from the dma-ranges. 93 $ref: /schemas/types.yaml#/definitions/uint64-array 94 items: 95 minItems: 1 96 maxItems: 3 97 98required: 99 - compatible 100 - reg 101 - ranges 102 - dma-ranges 103 - "#interrupt-cells" 104 - interrupts 105 - interrupt-names 106 - interrupt-map-mask 107 - interrupt-map 108 - msi-controller 109 110allOf: 111 - $ref: /schemas/pci/pci-bus.yaml# 112 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 113 - if: 114 properties: 115 compatible: 116 contains: 117 const: brcm,bcm4908-pcie 118 then: 119 properties: 120 resets: 121 items: 122 - description: reset controller handling the PERST# signal 123 124 reset-names: 125 items: 126 - const: perst 127 128 required: 129 - resets 130 - reset-names 131 - if: 132 properties: 133 compatible: 134 contains: 135 const: brcm,bcm7216-pcie 136 then: 137 properties: 138 resets: 139 items: 140 - description: phandle pointing to the RESCAL reset controller 141 142 reset-names: 143 items: 144 - const: rescal 145 146 required: 147 - resets 148 - reset-names 149 150unevaluatedProperties: false 151 152examples: 153 - | 154 #include <dt-bindings/interrupt-controller/irq.h> 155 #include <dt-bindings/interrupt-controller/arm-gic.h> 156 157 scb { 158 #address-cells = <2>; 159 #size-cells = <1>; 160 pcie0: pcie@7d500000 { 161 compatible = "brcm,bcm2711-pcie"; 162 reg = <0x0 0x7d500000 0x9310>; 163 device_type = "pci"; 164 #address-cells = <3>; 165 #size-cells = <2>; 166 #interrupt-cells = <1>; 167 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-names = "pcie", "msi"; 170 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 171 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 172 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 173 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 174 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 175 176 msi-parent = <&pcie0>; 177 msi-controller; 178 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; 179 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, 180 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; 181 brcm,enable-ssc; 182 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; 183 184 /* PCIe bridge, Root Port */ 185 pci@0,0 { 186 #address-cells = <3>; 187 #size-cells = <2>; 188 reg = <0x0 0x0 0x0 0x0 0x0>; 189 compatible = "pciclass,0604"; 190 device_type = "pci"; 191 vpcie3v3-supply = <&vreg7>; 192 ranges; 193 194 /* PCIe endpoint */ 195 pci-ep@0,0 { 196 assigned-addresses = 197 <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; 198 reg = <0x0 0x0 0x0 0x0 0x0>; 199 compatible = "pci14e4,1688"; 200 }; 201 }; 202 }; 203 }; 204