1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom iProc PCIe controller with the platform bus interface 8 9maintainers: 10 - Ray Jui <ray.jui@broadcom.com> 11 - Scott Branden <scott.branden@broadcom.com> 12 13allOf: 14 - $ref: /schemas/pci/pci-bus.yaml# 15 16properties: 17 compatible: 18 items: 19 - enum: 20 # for the first generation of PAXB based controller, used in SoCs 21 # including NSP, Cygnus, NS2, and Pegasus 22 - brcm,iproc-pcie 23 # for the second generation of PAXB-based controllers, used in 24 # Stingray 25 - brcm,iproc-pcie-paxb-v2 26 # For the first generation of PAXC based controller, used in NS2 27 - brcm,iproc-pcie-paxc 28 # For the second generation of PAXC based controller, used in Stingray 29 - brcm,iproc-pcie-paxc-v2 30 31 reg: 32 maxItems: 1 33 description: > 34 Base address and length of the PCIe controller I/O register space 35 36 ranges: 37 minItems: 1 38 maxItems: 2 39 description: > 40 Ranges for the PCI memory and I/O regions 41 42 phys: 43 maxItems: 1 44 45 phy-names: 46 items: 47 - const: pcie-phy 48 49 dma-coherent: true 50 51 brcm,pcie-ob: 52 type: boolean 53 description: > 54 Some iProc SoCs do not have the outbound address mapping done by the 55 ASIC after power on reset. In this case, SW needs to configure it 56 57 brcm,pcie-ob-axi-offset: 58 $ref: /schemas/types.yaml#/definitions/uint32 59 description: > 60 The offset from the AXI address to the internal address used by the 61 iProc PCIe core (not the PCIe address) 62 63 msi: 64 type: object 65 $ref: /schemas/interrupt-controller/msi-controller.yaml# 66 unevaluatedProperties: false 67 68 properties: 69 compatible: 70 items: 71 - const: brcm,iproc-msi 72 73 interrupts: 74 maxItems: 4 75 76 brcm,pcie-msi-inten: 77 type: boolean 78 description: 79 Needs to be present for some older iProc platforms that require the 80 interrupt enable registers to be set explicitly to enable MSI 81 82 msi-parent: true 83 84dependencies: 85 brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"] 86 brcm,pcie-msi-inten: [msi-controller] 87 88required: 89 - compatible 90 - reg 91 - ranges 92 93if: 94 properties: 95 compatible: 96 contains: 97 enum: 98 - brcm,iproc-pcie 99then: 100 required: 101 - interrupt-map 102 - interrupt-map-mask 103 104unevaluatedProperties: false 105 106examples: 107 - | 108 #include <dt-bindings/interrupt-controller/arm-gic.h> 109 110 gic: interrupt-controller { 111 interrupt-controller; 112 #interrupt-cells = <3>; 113 }; 114 115 pcie@18012000 { 116 compatible = "brcm,iproc-pcie"; 117 reg = <0x18012000 0x1000>; 118 119 #interrupt-cells = <1>; 120 interrupt-map-mask = <0 0 0 0>; 121 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; 122 123 linux,pci-domain = <0>; 124 125 bus-range = <0x00 0xff>; 126 127 #address-cells = <3>; 128 #size-cells = <2>; 129 device_type = "pci"; 130 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, 131 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 132 133 phys = <&phy 0 5>; 134 phy-names = "pcie-phy"; 135 136 brcm,pcie-ob; 137 brcm,pcie-ob-axi-offset = <0x00000000>; 138 139 msi-parent = <&msi0>; 140 141 /* iProc event queue based MSI */ 142 msi0: msi { 143 compatible = "brcm,iproc-msi"; 144 msi-controller; 145 interrupt-parent = <&gic>; 146 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, 147 <GIC_SPI 97 IRQ_TYPE_NONE>, 148 <GIC_SPI 98 IRQ_TYPE_NONE>, 149 <GIC_SPI 99 IRQ_TYPE_NONE>; 150 }; 151 }; 152 - | 153 pcie@18013000 { 154 compatible = "brcm,iproc-pcie"; 155 reg = <0x18013000 0x1000>; 156 157 #interrupt-cells = <1>; 158 interrupt-map-mask = <0 0 0 0>; 159 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; 160 161 linux,pci-domain = <1>; 162 163 bus-range = <0x00 0xff>; 164 165 #address-cells = <3>; 166 #size-cells = <2>; 167 device_type = "pci"; 168 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, 169 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 170 171 phys = <&phy 1 6>; 172 phy-names = "pcie-phy"; 173 }; 174