1* Broadcom iProc PCIe controller with the platform bus interface 2 3Required properties: 4- compatible: 5 "brcm,iproc-pcie" for the first generation of PAXB based controller, 6used in SoCs including NSP, Cygnus, NS2, and Pegasus 7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based 8controllers, used in Stingray 9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based 10controller, used in NS2 11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based 12controller, used in Stingray 13 PAXB-based root complex is used for external endpoint devices. PAXC-based 14root complex is connected to emulated endpoint devices internal to the ASIC 15- reg: base address and length of the PCIe controller I/O register space 16- #interrupt-cells: set to <1> 17- interrupt-map-mask and interrupt-map, standard PCI properties to define the 18 mapping of the PCIe interface to interrupt numbers 19- linux,pci-domain: PCI domain ID. Should be unique for each host controller 20- bus-range: PCI bus numbers covered 21- #address-cells: set to <3> 22- #size-cells: set to <2> 23- device_type: set to "pci" 24- ranges: ranges for the PCI memory and I/O regions 25 26Optional properties: 27- phys: phandle of the PCIe PHY device 28- phy-names: must be "pcie-phy" 29- dma-coherent: present if DMA operations are coherent 30- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done 31 by the ASIC after power on reset. In this case, SW is required to configure 32the mapping, based on inbound memory regions specified by this property. 33 34- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done 35by the ASIC after power on reset. In this case, SW needs to configure it 36 37If the brcm,pcie-ob property is present, the following properties become 38effective: 39 40Required: 41- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal 42address used by the iProc PCIe core (not the PCIe address) 43 44MSI support (optional): 45 46For older platforms without MSI integrated in the GIC, iProc PCIe core provides 47an event queue based MSI support. The iProc MSI uses host memories to store 48MSI posted writes in the event queues 49 50On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used 51 52- msi-map: Maps a Requester ID to an MSI controller and associated MSI 53sideband data 54 55- msi-parent: Link to the device node of the MSI controller, used when no MSI 56sideband data is passed between the iProc PCIe controller and the MSI 57controller 58 59Refer to the following binding documents for more detailed description on 60the use of 'msi-map' and 'msi-parent': 61 Documentation/devicetree/bindings/pci/pci-msi.txt 62 Documentation/devicetree/bindings/interrupt-controller/msi.txt 63 64When the iProc event queue based MSI is used, one needs to define the 65following properties in the MSI device node: 66- compatible: Must be "brcm,iproc-msi" 67- msi-controller: claims itself as an MSI controller 68- interrupts: List of interrupt IDs from its parent interrupt device 69 70Optional properties: 71- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that 72require the interrupt enable registers to be set explicitly to enable MSI 73 74Example: 75 pcie0: pcie@18012000 { 76 compatible = "brcm,iproc-pcie"; 77 reg = <0x18012000 0x1000>; 78 79 #interrupt-cells = <1>; 80 interrupt-map-mask = <0 0 0 0>; 81 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; 82 83 linux,pci-domain = <0>; 84 85 bus-range = <0x00 0xff>; 86 87 #address-cells = <3>; 88 #size-cells = <2>; 89 device_type = "pci"; 90 ranges = <0x81000000 0 0 0x28000000 0 0x00010000 91 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 92 93 phys = <&phy 0 5>; 94 phy-names = "pcie-phy"; 95 96 brcm,pcie-ob; 97 brcm,pcie-ob-axi-offset = <0x00000000>; 98 99 msi-parent = <&msi0>; 100 101 /* iProc event queue based MSI */ 102 msi0: msi@18012000 { 103 compatible = "brcm,iproc-msi"; 104 msi-controller; 105 interrupt-parent = <&gic>; 106 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, 107 <GIC_SPI 97 IRQ_TYPE_NONE>, 108 <GIC_SPI 98 IRQ_TYPE_NONE>, 109 <GIC_SPI 99 IRQ_TYPE_NONE>, 110 }; 111 }; 112 113 pcie1: pcie@18013000 { 114 compatible = "brcm,iproc-pcie"; 115 reg = <0x18013000 0x1000>; 116 117 #interrupt-cells = <1>; 118 interrupt-map-mask = <0 0 0 0>; 119 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; 120 121 linux,pci-domain = <1>; 122 123 bus-range = <0x00 0xff>; 124 125 #address-cells = <3>; 126 #size-cells = <2>; 127 device_type = "pci"; 128 ranges = <0x81000000 0 0 0x48000000 0 0x00010000 129 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 130 131 phys = <&phy 1 6>; 132 phy-names = "pcie-phy"; 133 }; 134