1* Axis ARTPEC-6 PCIe interface 2 3This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4and thus inherits all the common properties defined in designware-pcie.txt. 5 6Required properties: 7- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 11- reg: base addresses and lengths of the PCIe controller (DBI), 12 the PHY controller, and configuration address space. 13- reg-names: Must include the following entries: 14 - "dbi" 15 - "phy" 16 - "config" 17- interrupts: A list of interrupt outputs of the controller. Must contain an 18 entry for each entry in the interrupt-names property. 19- interrupt-names: Must include the following entries: 20 - "msi": The interrupt that is asserted when an MSI is received 21- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, 22 used to enable and control the Synopsys IP. 23 24Example: 25 26 pcie@f8050000 { 27 compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 28 reg = <0xf8050000 0x2000 29 0xf8040000 0x1000 30 0xc0000000 0x2000>; 31 reg-names = "dbi", "phy", "config"; 32 #address-cells = <3>; 33 #size-cells = <2>; 34 device_type = "pci"; 35 /* downstream I/O */ 36 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 37 /* non-prefetchable memory */ 38 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; 39 num-lanes = <2>; 40 bus-range = <0x00 0xff>; 41 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 42 interrupt-names = "msi"; 43 #interrupt-cells = <1>; 44 interrupt-map-mask = <0 0 0 0x7>; 45 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 46 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 47 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 48 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 49 axis,syscon-pcie = <&syscon>; 50 }; 51