1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Apple PCIe host controller 8 9maintainers: 10 - Mark Kettenis <kettenis@openbsd.org> 11 12description: | 13 The Apple PCIe host controller is a PCIe host controller with 14 multiple root ports present in Apple ARM SoC platforms, including 15 various iPhone and iPad devices and the "Apple Silicon" Macs. 16 The controller incorporates Synopsys DesigWare PCIe logic to 17 implements its root ports. But the ATU found on most DesignWare 18 PCIe host bridges is absent. 19 20 All root ports share a single ECAM space, but separate GPIOs are 21 used to take the PCI devices on those ports out of reset. Therefore 22 the standard "reset-gpios" and "max-link-speed" properties appear on 23 the child nodes that represent the PCI bridges that correspond to 24 the individual root ports. 25 26 MSIs are handled by the PCIe controller and translated into regular 27 interrupts. A range of 32 MSIs is provided. These 32 MSIs can be 28 distributed over the root ports as the OS sees fit by programming 29 the PCIe controller's port registers. 30 31properties: 32 compatible: 33 items: 34 - enum: 35 - apple,t8103-pcie 36 - apple,t6000-pcie 37 - const: apple,pcie 38 39 reg: 40 minItems: 3 41 maxItems: 6 42 43 reg-names: 44 minItems: 3 45 items: 46 - const: config 47 - const: rc 48 - const: port0 49 - const: port1 50 - const: port2 51 - const: port3 52 53 ranges: 54 minItems: 2 55 maxItems: 2 56 57 interrupts: 58 description: 59 Interrupt specifiers, one for each root port. 60 minItems: 1 61 maxItems: 4 62 63 msi-parent: true 64 65 msi-ranges: 66 maxItems: 1 67 68 iommu-map: true 69 iommu-map-mask: true 70 71required: 72 - compatible 73 - reg 74 - reg-names 75 - bus-range 76 - interrupts 77 - msi-controller 78 - msi-parent 79 - msi-ranges 80 81unevaluatedProperties: false 82 83allOf: 84 - $ref: /schemas/pci/pci-bus.yaml# 85 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 86 - if: 87 properties: 88 compatible: 89 contains: 90 const: apple,t8103-pcie 91 then: 92 properties: 93 reg: 94 maxItems: 5 95 interrupts: 96 maxItems: 3 97 98examples: 99 - | 100 #include <dt-bindings/interrupt-controller/apple-aic.h> 101 102 soc { 103 #address-cells = <2>; 104 #size-cells = <2>; 105 106 pcie0: pcie@690000000 { 107 compatible = "apple,t8103-pcie", "apple,pcie"; 108 device_type = "pci"; 109 110 reg = <0x6 0x90000000 0x0 0x1000000>, 111 <0x6 0x80000000 0x0 0x100000>, 112 <0x6 0x81000000 0x0 0x4000>, 113 <0x6 0x82000000 0x0 0x4000>, 114 <0x6 0x83000000 0x0 0x4000>; 115 reg-names = "config", "rc", "port0", "port1", "port2"; 116 117 interrupt-parent = <&aic>; 118 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 119 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 120 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 121 122 msi-controller; 123 msi-parent = <&pcie0>; 124 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 125 126 iommu-map = <0x100 &dart0 1 1>, 127 <0x200 &dart1 1 1>, 128 <0x300 &dart2 1 1>; 129 iommu-map-mask = <0xff00>; 130 131 bus-range = <0 3>; 132 #address-cells = <3>; 133 #size-cells = <2>; 134 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 135 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 136 137 power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; 138 pinctrl-0 = <&pcie_pins>; 139 pinctrl-names = "default"; 140 141 pci@0,0 { 142 device_type = "pci"; 143 reg = <0x0 0x0 0x0 0x0 0x0>; 144 reset-gpios = <&pinctrl_ap 152 0>; 145 146 #address-cells = <3>; 147 #size-cells = <2>; 148 ranges; 149 }; 150 151 pci@1,0 { 152 device_type = "pci"; 153 reg = <0x800 0x0 0x0 0x0 0x0>; 154 reset-gpios = <&pinctrl_ap 153 0>; 155 156 #address-cells = <3>; 157 #size-cells = <2>; 158 ranges; 159 }; 160 161 pci@2,0 { 162 device_type = "pci"; 163 reg = <0x1000 0x0 0x0 0x0 0x0>; 164 reset-gpios = <&pinctrl_ap 33 0>; 165 166 #address-cells = <3>; 167 #size-cells = <2>; 168 ranges; 169 }; 170 }; 171 }; 172