1Amlogic Meson AXG DWC PCIE SoC controller 2 3Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. 4It shares common functions with the PCIe DesignWare core driver and 5inherits common properties defined in 6Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 7 8Additional properties are described here: 9 10Required properties: 11- compatible: 12 should contain : 13 - "amlogic,axg-pcie" for AXG SoC Family 14 - "amlogic,g12a-pcie" for G12A SoC Family 15 to identify the core. 16- reg: 17 should contain the configuration address space. 18- reg-names: Must be 19 - "elbi" External local bus interface registers 20 - "cfg" Meson specific registers 21 - "config" PCIe configuration space 22- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. 23- clocks: Must contain an entry for each entry in clock-names. 24- clock-names: Must include the following entries: 25 - "pclk" PCIe GEN 100M PLL clock 26 - "port" PCIe_x(A or B) RC clock gate 27 - "general" PCIe Phy clock 28- resets: phandle to the reset lines. 29- reset-names: must contain "port" and "apb" 30 - "port" Port A or B reset 31 - "apb" Share APB reset 32- phys: should contain a phandle to the PCIE phy 33- phy-names: must contain "pcie" 34 35- device_type: 36 should be "pci". As specified in snps,dw-pcie.yaml 37 38 39Example configuration: 40 41 pcie: pcie@f9800000 { 42 compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 43 reg = <0x0 0xf9800000 0x0 0x400000 44 0x0 0xff646000 0x0 0x2000 45 0x0 0xf9f00000 0x0 0x100000>; 46 reg-names = "elbi", "cfg", "config"; 47 reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; 48 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 49 #interrupt-cells = <1>; 50 interrupt-map-mask = <0 0 0 0>; 51 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 52 bus-range = <0x0 0xff>; 53 #address-cells = <3>; 54 #size-cells = <2>; 55 device_type = "pci"; 56 ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; 57 58 clocks = <&clkc CLKID_USB 59 &clkc CLKID_PCIE_A 60 &clkc CLKID_PCIE_CML_EN0>; 61 clock-names = "general", 62 "pclk", 63 "port"; 64 resets = <&reset RESET_PCIE_A>, 65 <&reset RESET_PCIE_APB>; 66 reset-names = "port", 67 "apb"; 68 phys = <&pcie_phy>; 69 phy-names = "pcie"; 70 }; 71