1Generic OPP (Operating Performance Points) Bindings 2---------------------------------------------------- 3 4Devices work at voltage-current-frequency combinations and some implementations 5have the liberty of choosing these. These combinations are called Operating 6Performance Points aka OPPs. This document defines bindings for these OPPs 7applicable across wide range of devices. For illustration purpose, this document 8uses CPU as a device. 9 10This document contain multiple versions of OPP binding and only one of them 11should be used per device. 12 13Binding 1: operating-points 14============================ 15 16This binding only supports voltage-frequency pairs. 17 18Properties: 19- operating-points: An array of 2-tuples items, and each item consists 20 of frequency and voltage like <freq-kHz vol-uV>. 21 freq: clock frequency in kHz 22 vol: voltage in microvolt 23 24Examples: 25 26cpu@0 { 27 compatible = "arm,cortex-a9"; 28 reg = <0>; 29 next-level-cache = <&L2>; 30 operating-points = < 31 /* kHz uV */ 32 792000 1100000 33 396000 950000 34 198000 850000 35 >; 36}; 37 38 39Binding 2: operating-points-v2 40============================ 41 42* Property: operating-points-v2 43 44Devices supporting OPPs must set their "operating-points-v2" property with 45phandle to a OPP table in their DT node. The OPP core will use this phandle to 46find the operating points for the device. 47 48This can contain more than one phandle for power domain providers that provide 49multiple power domains. That is, one phandle for each power domain. If only one 50phandle is available, then the same OPP table will be used for all power domains 51provided by the power domain provider. 52 53If required, this can be extended for SoC vendor specific bindings. Such bindings 54should be documented as Documentation/devicetree/bindings/power/<vendor>-opp.txt 55and should have a compatible description like: "operating-points-v2-<vendor>". 56 57* OPP Table Node 58 59This describes the OPPs belonging to a device. This node can have following 60properties: 61 62Required properties: 63- compatible: Allow OPPs to express their compatibility. It should be: 64 "operating-points-v2". 65 66- OPP nodes: One or more OPP nodes describing voltage-current-frequency 67 combinations. Their name isn't significant but their phandle can be used to 68 reference an OPP. 69 70Optional properties: 71- opp-shared: Indicates that device nodes using this OPP Table Node's phandle 72 switch their DVFS state together, i.e. they share clock/voltage/current lines. 73 Missing property means devices have independent clock/voltage/current lines, 74 but they share OPP tables. 75 76- status: Marks the OPP table enabled/disabled. 77 78 79* OPP Node 80 81This defines voltage-current-frequency combinations along with other related 82properties. 83 84Required properties: 85- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a 86 required property for all device nodes, unless another "required" property to 87 uniquely identify the OPP nodes exists. Devices like power domains must have 88 another (implementation dependent) property. 89 90- opp-peak-kBps: Peak bandwidth in kilobytes per second, expressed as an array 91 of 32-bit big-endian integers. Each element of the array represents the 92 peak bandwidth value of each interconnect path. The number of elements should 93 match the number of interconnect paths. 94 95Optional properties: 96- opp-microvolt: voltage in micro Volts. 97 98 A single regulator's voltage is specified with an array of size one or three. 99 Single entry is for target voltage and three entries are for <target min max> 100 voltages. 101 102 Entries for multiple regulators shall be provided in the same field separated 103 by angular brackets <>. The OPP binding doesn't provide any provisions to 104 relate the values to their power supplies or the order in which the supplies 105 need to be configured and that is left for the implementation specific 106 binding. 107 108 Entries for all regulators shall be of the same size, i.e. either all use a 109 single value or triplets. 110 111- opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to 112 the above opp-microvolt property, but allows multiple voltage ranges to be 113 provided for the same OPP. At runtime, the platform can pick a <name> and 114 matching opp-microvolt-<name> property will be enabled for all OPPs. If the 115 platform doesn't pick a specific <name> or the <name> doesn't match with any 116 opp-microvolt-<name> properties, then opp-microvolt property shall be used, if 117 present. 118 119- opp-microamp: The maximum current drawn by the device in microamperes 120 considering system specific parameters (such as transients, process, aging, 121 maximum operating temperature range etc.) as necessary. This may be used to 122 set the most efficient regulator operating mode. 123 124 Should only be set if opp-microvolt is set for the OPP. 125 126 Entries for multiple regulators shall be provided in the same field separated 127 by angular brackets <>. If current values aren't required for a regulator, 128 then it shall be filled with 0. If current values aren't required for any of 129 the regulators, then this field is not required. The OPP binding doesn't 130 provide any provisions to relate the values to their power supplies or the 131 order in which the supplies need to be configured and that is left for the 132 implementation specific binding. 133 134- opp-microamp-<name>: Named opp-microamp property. Similar to 135 opp-microvolt-<name> property, but for microamp instead. 136 137- opp-level: A value representing the performance level of the device, 138 expressed as a 32-bit integer. 139 140- opp-avg-kBps: Average bandwidth in kilobytes per second, expressed as an array 141 of 32-bit big-endian integers. Each element of the array represents the 142 average bandwidth value of each interconnect path. The number of elements 143 should match the number of interconnect paths. This property is only 144 meaningful in OPP tables where opp-peak-kBps is present. 145 146- clock-latency-ns: Specifies the maximum possible transition latency (in 147 nanoseconds) for switching to this OPP from any other OPP. 148 149- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is 150 available on some platforms, where the device can run over its operating 151 frequency for a short duration of time limited by the device's power, current 152 and thermal limits. 153 154- opp-suspend: Marks the OPP to be used during device suspend. If multiple OPPs 155 in the table have this, the OPP with highest opp-hz will be used. 156 157- opp-supported-hw: This enables us to select only a subset of OPPs from the 158 larger OPP table, based on what version of the hardware we are running on. We 159 still can't have multiple nodes with the same opp-hz value in OPP table. 160 161 It's a user defined array containing a hierarchy of hardware version numbers, 162 supported by the OPP. For example: a platform with hierarchy of three levels 163 of versions (A, B and C), this field should be like <X Y Z>, where X 164 corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z 165 corresponds to version hierarchy C. 166 167 Each level of hierarchy is represented by a 32 bit value, and so there can be 168 only 32 different supported version per hierarchy. i.e. 1 bit per version. A 169 value of 0xFFFFFFFF will enable the OPP for all versions for that hierarchy 170 level. And a value of 0x00000000 will disable the OPP completely, and so we 171 never want that to happen. 172 173 If 32 values aren't sufficient for a version hierarchy, than that version 174 hierarchy can be contained in multiple 32 bit values. i.e. <X Y Z1 Z2> in the 175 above example, Z1 & Z2 refer to the version hierarchy Z. 176 177- status: Marks the node enabled/disabled. 178 179- required-opps: This contains phandle to an OPP node in another device's OPP 180 table. It may contain an array of phandles, where each phandle points to an 181 OPP of a different device. It should not contain multiple phandles to the OPP 182 nodes in the same OPP table. This specifies the minimum required OPP of the 183 device(s), whose OPP's phandle is present in this property, for the 184 functioning of the current device at the current OPP (where this property is 185 present). 186 187Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. 188 189/ { 190 cpus { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 194 cpu@0 { 195 compatible = "arm,cortex-a9"; 196 reg = <0>; 197 next-level-cache = <&L2>; 198 clocks = <&clk_controller 0>; 199 clock-names = "cpu"; 200 cpu-supply = <&cpu_supply0>; 201 operating-points-v2 = <&cpu0_opp_table>; 202 }; 203 204 cpu@1 { 205 compatible = "arm,cortex-a9"; 206 reg = <1>; 207 next-level-cache = <&L2>; 208 clocks = <&clk_controller 0>; 209 clock-names = "cpu"; 210 cpu-supply = <&cpu_supply0>; 211 operating-points-v2 = <&cpu0_opp_table>; 212 }; 213 }; 214 215 cpu0_opp_table: opp_table0 { 216 compatible = "operating-points-v2"; 217 opp-shared; 218 219 opp-1000000000 { 220 opp-hz = /bits/ 64 <1000000000>; 221 opp-microvolt = <975000 970000 985000>; 222 opp-microamp = <70000>; 223 clock-latency-ns = <300000>; 224 opp-suspend; 225 }; 226 opp-1100000000 { 227 opp-hz = /bits/ 64 <1100000000>; 228 opp-microvolt = <1000000 980000 1010000>; 229 opp-microamp = <80000>; 230 clock-latency-ns = <310000>; 231 }; 232 opp-1200000000 { 233 opp-hz = /bits/ 64 <1200000000>; 234 opp-microvolt = <1025000>; 235 clock-latency-ns = <290000>; 236 turbo-mode; 237 }; 238 }; 239}; 240 241Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states 242independently. 243 244/ { 245 cpus { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 cpu@0 { 250 compatible = "qcom,krait"; 251 reg = <0>; 252 next-level-cache = <&L2>; 253 clocks = <&clk_controller 0>; 254 clock-names = "cpu"; 255 cpu-supply = <&cpu_supply0>; 256 operating-points-v2 = <&cpu_opp_table>; 257 }; 258 259 cpu@1 { 260 compatible = "qcom,krait"; 261 reg = <1>; 262 next-level-cache = <&L2>; 263 clocks = <&clk_controller 1>; 264 clock-names = "cpu"; 265 cpu-supply = <&cpu_supply1>; 266 operating-points-v2 = <&cpu_opp_table>; 267 }; 268 269 cpu@2 { 270 compatible = "qcom,krait"; 271 reg = <2>; 272 next-level-cache = <&L2>; 273 clocks = <&clk_controller 2>; 274 clock-names = "cpu"; 275 cpu-supply = <&cpu_supply2>; 276 operating-points-v2 = <&cpu_opp_table>; 277 }; 278 279 cpu@3 { 280 compatible = "qcom,krait"; 281 reg = <3>; 282 next-level-cache = <&L2>; 283 clocks = <&clk_controller 3>; 284 clock-names = "cpu"; 285 cpu-supply = <&cpu_supply3>; 286 operating-points-v2 = <&cpu_opp_table>; 287 }; 288 }; 289 290 cpu_opp_table: opp_table { 291 compatible = "operating-points-v2"; 292 293 /* 294 * Missing opp-shared property means CPUs switch DVFS states 295 * independently. 296 */ 297 298 opp-1000000000 { 299 opp-hz = /bits/ 64 <1000000000>; 300 opp-microvolt = <975000 970000 985000>; 301 opp-microamp = <70000>; 302 clock-latency-ns = <300000>; 303 opp-suspend; 304 }; 305 opp-1100000000 { 306 opp-hz = /bits/ 64 <1100000000>; 307 opp-microvolt = <1000000 980000 1010000>; 308 opp-microamp = <80000>; 309 clock-latency-ns = <310000>; 310 }; 311 opp-1200000000 { 312 opp-hz = /bits/ 64 <1200000000>; 313 opp-microvolt = <1025000>; 314 opp-microamp = <90000; 315 lock-latency-ns = <290000>; 316 turbo-mode; 317 }; 318 }; 319}; 320 321Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch 322DVFS state together. 323 324/ { 325 cpus { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 cpu@0 { 330 compatible = "arm,cortex-a7"; 331 reg = <0>; 332 next-level-cache = <&L2>; 333 clocks = <&clk_controller 0>; 334 clock-names = "cpu"; 335 cpu-supply = <&cpu_supply0>; 336 operating-points-v2 = <&cluster0_opp>; 337 }; 338 339 cpu@1 { 340 compatible = "arm,cortex-a7"; 341 reg = <1>; 342 next-level-cache = <&L2>; 343 clocks = <&clk_controller 0>; 344 clock-names = "cpu"; 345 cpu-supply = <&cpu_supply0>; 346 operating-points-v2 = <&cluster0_opp>; 347 }; 348 349 cpu@100 { 350 compatible = "arm,cortex-a15"; 351 reg = <100>; 352 next-level-cache = <&L2>; 353 clocks = <&clk_controller 1>; 354 clock-names = "cpu"; 355 cpu-supply = <&cpu_supply1>; 356 operating-points-v2 = <&cluster1_opp>; 357 }; 358 359 cpu@101 { 360 compatible = "arm,cortex-a15"; 361 reg = <101>; 362 next-level-cache = <&L2>; 363 clocks = <&clk_controller 1>; 364 clock-names = "cpu"; 365 cpu-supply = <&cpu_supply1>; 366 operating-points-v2 = <&cluster1_opp>; 367 }; 368 }; 369 370 cluster0_opp: opp_table0 { 371 compatible = "operating-points-v2"; 372 opp-shared; 373 374 opp-1000000000 { 375 opp-hz = /bits/ 64 <1000000000>; 376 opp-microvolt = <975000 970000 985000>; 377 opp-microamp = <70000>; 378 clock-latency-ns = <300000>; 379 opp-suspend; 380 }; 381 opp-1100000000 { 382 opp-hz = /bits/ 64 <1100000000>; 383 opp-microvolt = <1000000 980000 1010000>; 384 opp-microamp = <80000>; 385 clock-latency-ns = <310000>; 386 }; 387 opp-1200000000 { 388 opp-hz = /bits/ 64 <1200000000>; 389 opp-microvolt = <1025000>; 390 opp-microamp = <90000>; 391 clock-latency-ns = <290000>; 392 turbo-mode; 393 }; 394 }; 395 396 cluster1_opp: opp_table1 { 397 compatible = "operating-points-v2"; 398 opp-shared; 399 400 opp-1300000000 { 401 opp-hz = /bits/ 64 <1300000000>; 402 opp-microvolt = <1050000 1045000 1055000>; 403 opp-microamp = <95000>; 404 clock-latency-ns = <400000>; 405 opp-suspend; 406 }; 407 opp-1400000000 { 408 opp-hz = /bits/ 64 <1400000000>; 409 opp-microvolt = <1075000>; 410 opp-microamp = <100000>; 411 clock-latency-ns = <400000>; 412 }; 413 opp-1500000000 { 414 opp-hz = /bits/ 64 <1500000000>; 415 opp-microvolt = <1100000 1010000 1110000>; 416 opp-microamp = <95000>; 417 clock-latency-ns = <400000>; 418 turbo-mode; 419 }; 420 }; 421}; 422 423Example 4: Handling multiple regulators 424 425/ { 426 cpus { 427 cpu@0 { 428 compatible = "vendor,cpu-type"; 429 ... 430 431 vcc0-supply = <&cpu_supply0>; 432 vcc1-supply = <&cpu_supply1>; 433 vcc2-supply = <&cpu_supply2>; 434 operating-points-v2 = <&cpu0_opp_table>; 435 }; 436 }; 437 438 cpu0_opp_table: opp_table0 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 opp-1000000000 { 443 opp-hz = /bits/ 64 <1000000000>; 444 opp-microvolt = <970000>, /* Supply 0 */ 445 <960000>, /* Supply 1 */ 446 <960000>; /* Supply 2 */ 447 opp-microamp = <70000>, /* Supply 0 */ 448 <70000>, /* Supply 1 */ 449 <70000>; /* Supply 2 */ 450 clock-latency-ns = <300000>; 451 }; 452 453 /* OR */ 454 455 opp-1000000000 { 456 opp-hz = /bits/ 64 <1000000000>; 457 opp-microvolt = <975000 970000 985000>, /* Supply 0 */ 458 <965000 960000 975000>, /* Supply 1 */ 459 <965000 960000 975000>; /* Supply 2 */ 460 opp-microamp = <70000>, /* Supply 0 */ 461 <70000>, /* Supply 1 */ 462 <70000>; /* Supply 2 */ 463 clock-latency-ns = <300000>; 464 }; 465 466 /* OR */ 467 468 opp-1000000000 { 469 opp-hz = /bits/ 64 <1000000000>; 470 opp-microvolt = <975000 970000 985000>, /* Supply 0 */ 471 <965000 960000 975000>, /* Supply 1 */ 472 <965000 960000 975000>; /* Supply 2 */ 473 opp-microamp = <70000>, /* Supply 0 */ 474 <0>, /* Supply 1 doesn't need this */ 475 <70000>; /* Supply 2 */ 476 clock-latency-ns = <300000>; 477 }; 478 }; 479}; 480 481Example 5: opp-supported-hw 482(example: three level hierarchy of versions: cuts, substrate and process) 483 484/ { 485 cpus { 486 cpu@0 { 487 compatible = "arm,cortex-a7"; 488 ... 489 490 cpu-supply = <&cpu_supply> 491 operating-points-v2 = <&cpu0_opp_table_slow>; 492 }; 493 }; 494 495 opp_table { 496 compatible = "operating-points-v2"; 497 opp-shared; 498 499 opp-600000000 { 500 /* 501 * Supports all substrate and process versions for 0xF 502 * cuts, i.e. only first four cuts. 503 */ 504 opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF> 505 opp-hz = /bits/ 64 <600000000>; 506 opp-microvolt = <915000 900000 925000>; 507 ... 508 }; 509 510 opp-800000000 { 511 /* 512 * Supports: 513 * - cuts: only one, 6th cut (represented by 6th bit). 514 * - substrate: supports 16 different substrate versions 515 * - process: supports 9 different process versions 516 */ 517 opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0> 518 opp-hz = /bits/ 64 <800000000>; 519 opp-microvolt = <915000 900000 925000>; 520 ... 521 }; 522 }; 523}; 524 525Example 6: opp-microvolt-<name>, opp-microamp-<name>: 526(example: device with two possible microvolt ranges: slow and fast) 527 528/ { 529 cpus { 530 cpu@0 { 531 compatible = "arm,cortex-a7"; 532 ... 533 534 operating-points-v2 = <&cpu0_opp_table>; 535 }; 536 }; 537 538 cpu0_opp_table: opp_table0 { 539 compatible = "operating-points-v2"; 540 opp-shared; 541 542 opp-1000000000 { 543 opp-hz = /bits/ 64 <1000000000>; 544 opp-microvolt-slow = <915000 900000 925000>; 545 opp-microvolt-fast = <975000 970000 985000>; 546 opp-microamp-slow = <70000>; 547 opp-microamp-fast = <71000>; 548 }; 549 550 opp-1200000000 { 551 opp-hz = /bits/ 64 <1200000000>; 552 opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */ 553 <925000 910000 935000>; /* Supply vcc1 */ 554 opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */ 555 <965000 960000 975000>; /* Supply vcc1 */ 556 opp-microamp = <70000>; /* Will be used for both slow/fast */ 557 }; 558 }; 559}; 560