1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic OPP (Operating Performance Points) Bindings 8 9maintainers: 10 - Viresh Kumar <viresh.kumar@linaro.org> 11 12allOf: 13 - $ref: opp-v2-base.yaml# 14 15properties: 16 compatible: 17 const: operating-points-v2 18 19unevaluatedProperties: false 20 21examples: 22 - | 23 /* 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states 25 * together. 26 */ 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 compatible = "arm,cortex-a9"; 33 device_type = "cpu"; 34 reg = <0>; 35 next-level-cache = <&L2>; 36 clocks = <&clk_controller 0>; 37 clock-names = "cpu"; 38 cpu-supply = <&cpu_supply0>; 39 operating-points-v2 = <&cpu0_opp_table0>; 40 }; 41 42 cpu@1 { 43 compatible = "arm,cortex-a9"; 44 device_type = "cpu"; 45 reg = <1>; 46 next-level-cache = <&L2>; 47 clocks = <&clk_controller 0>; 48 clock-names = "cpu"; 49 cpu-supply = <&cpu_supply0>; 50 operating-points-v2 = <&cpu0_opp_table0>; 51 }; 52 }; 53 54 cpu0_opp_table0: opp-table { 55 compatible = "operating-points-v2"; 56 opp-shared; 57 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <975000 970000 985000>; 61 opp-microamp = <70000>; 62 clock-latency-ns = <300000>; 63 opp-suspend; 64 }; 65 opp-1100000000 { 66 opp-hz = /bits/ 64 <1100000000>; 67 opp-microvolt = <1000000 980000 1010000>; 68 opp-microamp = <80000>; 69 clock-latency-ns = <310000>; 70 }; 71 opp-1200000000 { 72 opp-hz = /bits/ 64 <1200000000>; 73 opp-microvolt = <1025000>; 74 clock-latency-ns = <290000>; 75 turbo-mode; 76 }; 77 }; 78 79 - | 80 /* 81 * Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states 82 * independently. 83 */ 84 cpus { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 cpu@0 { 89 compatible = "qcom,krait"; 90 device_type = "cpu"; 91 reg = <0>; 92 next-level-cache = <&L2>; 93 clocks = <&clk_controller 0>; 94 clock-names = "cpu"; 95 cpu-supply = <&cpu_supply0>; 96 operating-points-v2 = <&cpu_opp_table>; 97 }; 98 99 cpu@1 { 100 compatible = "qcom,krait"; 101 device_type = "cpu"; 102 reg = <1>; 103 next-level-cache = <&L2>; 104 clocks = <&clk_controller 1>; 105 clock-names = "cpu"; 106 cpu-supply = <&cpu_supply1>; 107 operating-points-v2 = <&cpu_opp_table>; 108 }; 109 110 cpu@2 { 111 compatible = "qcom,krait"; 112 device_type = "cpu"; 113 reg = <2>; 114 next-level-cache = <&L2>; 115 clocks = <&clk_controller 2>; 116 clock-names = "cpu"; 117 cpu-supply = <&cpu_supply2>; 118 operating-points-v2 = <&cpu_opp_table>; 119 }; 120 121 cpu@3 { 122 compatible = "qcom,krait"; 123 device_type = "cpu"; 124 reg = <3>; 125 next-level-cache = <&L2>; 126 clocks = <&clk_controller 3>; 127 clock-names = "cpu"; 128 cpu-supply = <&cpu_supply3>; 129 operating-points-v2 = <&cpu_opp_table>; 130 }; 131 }; 132 133 cpu_opp_table: opp-table { 134 compatible = "operating-points-v2"; 135 136 /* 137 * Missing opp-shared property means CPUs switch DVFS states 138 * independently. 139 */ 140 141 opp-1000000000 { 142 opp-hz = /bits/ 64 <1000000000>; 143 opp-microvolt = <975000 970000 985000>; 144 opp-microamp = <70000>; 145 clock-latency-ns = <300000>; 146 opp-suspend; 147 }; 148 opp-1100000000 { 149 opp-hz = /bits/ 64 <1100000000>; 150 opp-microvolt = <1000000 980000 1010000>; 151 opp-microamp = <80000>; 152 clock-latency-ns = <310000>; 153 }; 154 opp-1200000000 { 155 opp-hz = /bits/ 64 <1200000000>; 156 opp-microvolt = <1025000>; 157 opp-microamp = <90000>; 158 lock-latency-ns = <290000>; 159 turbo-mode; 160 }; 161 }; 162 163 - | 164 /* 165 * Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch 166 * DVFS state together. 167 */ 168 cpus { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 cpu@0 { 173 compatible = "arm,cortex-a7"; 174 device_type = "cpu"; 175 reg = <0>; 176 next-level-cache = <&L2>; 177 clocks = <&clk_controller 0>; 178 clock-names = "cpu"; 179 cpu-supply = <&cpu_supply0>; 180 operating-points-v2 = <&cluster0_opp>; 181 }; 182 183 cpu@1 { 184 compatible = "arm,cortex-a7"; 185 device_type = "cpu"; 186 reg = <1>; 187 next-level-cache = <&L2>; 188 clocks = <&clk_controller 0>; 189 clock-names = "cpu"; 190 cpu-supply = <&cpu_supply0>; 191 operating-points-v2 = <&cluster0_opp>; 192 }; 193 194 cpu@100 { 195 compatible = "arm,cortex-a15"; 196 device_type = "cpu"; 197 reg = <100>; 198 next-level-cache = <&L2>; 199 clocks = <&clk_controller 1>; 200 clock-names = "cpu"; 201 cpu-supply = <&cpu_supply1>; 202 operating-points-v2 = <&cluster1_opp>; 203 }; 204 205 cpu@101 { 206 compatible = "arm,cortex-a15"; 207 device_type = "cpu"; 208 reg = <101>; 209 next-level-cache = <&L2>; 210 clocks = <&clk_controller 1>; 211 clock-names = "cpu"; 212 cpu-supply = <&cpu_supply1>; 213 operating-points-v2 = <&cluster1_opp>; 214 }; 215 }; 216 217 cluster0_opp: opp-table-0 { 218 compatible = "operating-points-v2"; 219 opp-shared; 220 221 opp-1000000000 { 222 opp-hz = /bits/ 64 <1000000000>; 223 opp-microvolt = <975000 970000 985000>; 224 opp-microamp = <70000>; 225 clock-latency-ns = <300000>; 226 opp-suspend; 227 }; 228 opp-1100000000 { 229 opp-hz = /bits/ 64 <1100000000>; 230 opp-microvolt = <1000000 980000 1010000>; 231 opp-microamp = <80000>; 232 clock-latency-ns = <310000>; 233 }; 234 opp-1200000000 { 235 opp-hz = /bits/ 64 <1200000000>; 236 opp-microvolt = <1025000>; 237 opp-microamp = <90000>; 238 clock-latency-ns = <290000>; 239 turbo-mode; 240 }; 241 }; 242 243 cluster1_opp: opp-table-1 { 244 compatible = "operating-points-v2"; 245 opp-shared; 246 247 opp-1300000000 { 248 opp-hz = /bits/ 64 <1300000000>; 249 opp-microvolt = <1050000 1045000 1055000>; 250 opp-microamp = <95000>; 251 clock-latency-ns = <400000>; 252 opp-suspend; 253 }; 254 opp-1400000000 { 255 opp-hz = /bits/ 64 <1400000000>; 256 opp-microvolt = <1075000>; 257 opp-microamp = <100000>; 258 clock-latency-ns = <400000>; 259 }; 260 opp-1500000000 { 261 opp-hz = /bits/ 64 <1500000000>; 262 opp-microvolt = <1100000 1010000 1110000>; 263 opp-microamp = <95000>; 264 clock-latency-ns = <400000>; 265 turbo-mode; 266 }; 267 }; 268 269 - | 270 /* Example 4: Handling multiple regulators */ 271 cpus { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 cpu@0 { 276 compatible = "foo,cpu-type"; 277 device_type = "cpu"; 278 reg = <0>; 279 280 vcc0-supply = <&cpu_supply0>; 281 vcc1-supply = <&cpu_supply1>; 282 vcc2-supply = <&cpu_supply2>; 283 operating-points-v2 = <&cpu0_opp_table4>; 284 }; 285 }; 286 287 cpu0_opp_table4: opp-table-0 { 288 compatible = "operating-points-v2"; 289 opp-shared; 290 291 opp-1000000000 { 292 opp-hz = /bits/ 64 <1000000000>; 293 opp-microvolt = <970000>, /* Supply 0 */ 294 <960000>, /* Supply 1 */ 295 <960000>; /* Supply 2 */ 296 opp-microamp = <70000>, /* Supply 0 */ 297 <70000>, /* Supply 1 */ 298 <70000>; /* Supply 2 */ 299 clock-latency-ns = <300000>; 300 }; 301 302 /* OR */ 303 304 opp-1000000001 { 305 opp-hz = /bits/ 64 <1000000001>; 306 opp-microvolt = <975000 970000 985000>, /* Supply 0 */ 307 <965000 960000 975000>, /* Supply 1 */ 308 <965000 960000 975000>; /* Supply 2 */ 309 opp-microamp = <70000>, /* Supply 0 */ 310 <70000>, /* Supply 1 */ 311 <70000>; /* Supply 2 */ 312 clock-latency-ns = <300000>; 313 }; 314 315 /* OR */ 316 317 opp-1000000002 { 318 opp-hz = /bits/ 64 <1000000002>; 319 opp-microvolt = <975000 970000 985000>, /* Supply 0 */ 320 <965000 960000 975000>, /* Supply 1 */ 321 <965000 960000 975000>; /* Supply 2 */ 322 opp-microamp = <70000>, /* Supply 0 */ 323 <0>, /* Supply 1 doesn't need this */ 324 <70000>; /* Supply 2 */ 325 clock-latency-ns = <300000>; 326 }; 327 }; 328 329 - | 330 /* 331 * Example 5: opp-supported-hw 332 * (example: three level hierarchy of versions: cuts, substrate and process) 333 */ 334 cpus { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 338 cpu@0 { 339 compatible = "arm,cortex-a7"; 340 device_type = "cpu"; 341 reg = <0>; 342 cpu-supply = <&cpu_supply>; 343 operating-points-v2 = <&cpu0_opp_table_slow>; 344 }; 345 }; 346 347 cpu0_opp_table_slow: opp-table { 348 compatible = "operating-points-v2"; 349 opp-shared; 350 351 opp-600000000 { 352 /* 353 * Supports all substrate and process versions for 0xF 354 * cuts, i.e. only first four cuts. 355 */ 356 opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>; 357 opp-hz = /bits/ 64 <600000000>; 358 }; 359 360 opp-800000000 { 361 /* 362 * Supports: 363 * - cuts: only one, 6th cut (represented by 6th bit). 364 * - substrate: supports 16 different substrate versions 365 * - process: supports 9 different process versions 366 */ 367 opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>; 368 opp-hz = /bits/ 64 <800000000>; 369 }; 370 371 opp-900000000 { 372 /* 373 * Supports: 374 * - All cuts and substrate where process version is 0x2. 375 * - All cuts and process where substrate version is 0x2. 376 */ 377 opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>, 378 <0xFFFFFFFF 0x01 0xFFFFFFFF>; 379 opp-hz = /bits/ 64 <900000000>; 380 }; 381 }; 382 383 - | 384 /* 385 * Example 6: opp-microvolt-<name>, opp-microamp-<name>: 386 * (example: device with two possible microvolt ranges: slow and fast) 387 */ 388 cpus { 389 #address-cells = <1>; 390 #size-cells = <0>; 391 392 cpu@0 { 393 compatible = "arm,cortex-a7"; 394 device_type = "cpu"; 395 reg = <0>; 396 operating-points-v2 = <&cpu0_opp_table6>; 397 }; 398 }; 399 400 cpu0_opp_table6: opp-table-0 { 401 compatible = "operating-points-v2"; 402 opp-shared; 403 404 opp-1000000000 { 405 opp-hz = /bits/ 64 <1000000000>; 406 opp-microvolt-slow = <915000 900000 925000>; 407 opp-microvolt-fast = <975000 970000 985000>; 408 opp-microamp-slow = <70000>; 409 opp-microamp-fast = <71000>; 410 }; 411 412 opp-1200000000 { 413 opp-hz = /bits/ 64 <1200000000>; 414 opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */ 415 <925000 910000 935000>; /* Supply vcc1 */ 416 opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */ 417 <965000 960000 975000>; /* Supply vcc1 */ 418 opp-microamp = <70000>; /* Will be used for both slow/fast */ 419 }; 420 }; 421 422 - | 423 /* 424 * Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware, 425 * distinct clock controls but two sets of clock/voltage/current lines. 426 */ 427 cpus { 428 #address-cells = <2>; 429 #size-cells = <0>; 430 431 cpu@0 { 432 compatible = "arm,cortex-a53"; 433 device_type = "cpu"; 434 reg = <0x0 0x100>; 435 next-level-cache = <&A53_L2>; 436 clocks = <&dvfs_controller 0>; 437 operating-points-v2 = <&cpu_opp0_table>; 438 }; 439 cpu@1 { 440 compatible = "arm,cortex-a53"; 441 device_type = "cpu"; 442 reg = <0x0 0x101>; 443 next-level-cache = <&A53_L2>; 444 clocks = <&dvfs_controller 1>; 445 operating-points-v2 = <&cpu_opp0_table>; 446 }; 447 cpu@2 { 448 compatible = "arm,cortex-a53"; 449 device_type = "cpu"; 450 reg = <0x0 0x102>; 451 next-level-cache = <&A53_L2>; 452 clocks = <&dvfs_controller 2>; 453 operating-points-v2 = <&cpu_opp1_table>; 454 }; 455 cpu@3 { 456 compatible = "arm,cortex-a53"; 457 device_type = "cpu"; 458 reg = <0x0 0x103>; 459 next-level-cache = <&A53_L2>; 460 clocks = <&dvfs_controller 3>; 461 operating-points-v2 = <&cpu_opp1_table>; 462 }; 463 464 }; 465 466 cpu_opp0_table: opp-table-0 { 467 compatible = "operating-points-v2"; 468 opp-shared; 469 }; 470 471 cpu_opp1_table: opp-table-1 { 472 compatible = "operating-points-v2"; 473 opp-shared; 474 }; 475... 476