1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. NVMEM OPP bindings 8 9maintainers: 10 - Ilia Lin <ilia.lin@kernel.org> 11 12allOf: 13 - $ref: opp-v2-base.yaml# 14 15description: | 16 In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996, 17 the CPU frequencies subset and voltage value of each OPP varies based on 18 the silicon variant in use. 19 Qualcomm Technologies, Inc. Process Voltage Scaling Tables 20 defines the voltage and frequency value based on the speedbin blown in 21 the efuse combination. 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). 24 This is used to determine the voltage and frequency value for each OPP of 25 operating-points-v2 table when it is parsed by the OPP framework. 26 27properties: 28 compatible: 29 const: operating-points-v2-kryo-cpu 30 31 nvmem-cells: 32 description: | 33 A phandle pointing to a nvmem-cells node representing the 34 efuse registers that has information about the 35 speedbin that is used to select the right frequency/voltage 36 value pair. 37 38 opp-shared: true 39 40patternProperties: 41 '^opp-?[0-9]+$': 42 type: object 43 additionalProperties: false 44 45 properties: 46 opp-hz: true 47 48 opp-microvolt: true 49 50 opp-supported-hw: 51 description: | 52 A single 32 bit bitmap value, representing compatible HW. 53 Bitmap: 54 0: MSM8996, speedbin 0 55 1: MSM8996, speedbin 1 56 2: MSM8996, speedbin 2 57 3-31: unused 58 maximum: 0x7 59 60 clock-latency-ns: true 61 62 required-opps: true 63 64 required: 65 - opp-hz 66 67required: 68 - compatible 69 70if: 71 required: 72 - nvmem-cells 73then: 74 patternProperties: 75 '^opp-?[0-9]+$': 76 required: 77 - opp-supported-hw 78 79additionalProperties: false 80 81examples: 82 - | 83 / { 84 model = "Qualcomm Technologies, Inc. DB820c"; 85 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; 86 #address-cells = <2>; 87 #size-cells = <2>; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 cpu-idle-states = <&CPU_SLEEP_0>; 99 capacity-dmips-mhz = <1024>; 100 clocks = <&kryocc 0>; 101 operating-points-v2 = <&cluster0_opp>; 102 power-domains = <&cpr>; 103 power-domain-names = "cpr"; 104 #cooling-cells = <2>; 105 next-level-cache = <&L2_0>; 106 L2_0: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 }; 110 }; 111 112 CPU1: cpu@1 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo"; 115 reg = <0x0 0x1>; 116 enable-method = "psci"; 117 cpu-idle-states = <&CPU_SLEEP_0>; 118 capacity-dmips-mhz = <1024>; 119 clocks = <&kryocc 0>; 120 operating-points-v2 = <&cluster0_opp>; 121 power-domains = <&cpr>; 122 power-domain-names = "cpr"; 123 #cooling-cells = <2>; 124 next-level-cache = <&L2_0>; 125 }; 126 127 CPU2: cpu@100 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo"; 130 reg = <0x0 0x100>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 capacity-dmips-mhz = <1024>; 134 clocks = <&kryocc 1>; 135 operating-points-v2 = <&cluster1_opp>; 136 power-domains = <&cpr>; 137 power-domain-names = "cpr"; 138 #cooling-cells = <2>; 139 next-level-cache = <&L2_1>; 140 L2_1: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 }; 144 }; 145 146 CPU3: cpu@101 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo"; 149 reg = <0x0 0x101>; 150 enable-method = "psci"; 151 cpu-idle-states = <&CPU_SLEEP_0>; 152 capacity-dmips-mhz = <1024>; 153 clocks = <&kryocc 1>; 154 operating-points-v2 = <&cluster1_opp>; 155 power-domains = <&cpr>; 156 power-domain-names = "cpr"; 157 #cooling-cells = <2>; 158 next-level-cache = <&L2_1>; 159 }; 160 161 cpu-map { 162 cluster0 { 163 core0 { 164 cpu = <&CPU0>; 165 }; 166 167 core1 { 168 cpu = <&CPU1>; 169 }; 170 }; 171 172 cluster1 { 173 core0 { 174 cpu = <&CPU2>; 175 }; 176 177 core1 { 178 cpu = <&CPU3>; 179 }; 180 }; 181 }; 182 }; 183 184 cluster0_opp: opp-table-0 { 185 compatible = "operating-points-v2-kryo-cpu"; 186 nvmem-cells = <&speedbin_efuse>; 187 opp-shared; 188 189 opp-307200000 { 190 opp-hz = /bits/ 64 <307200000>; 191 opp-microvolt = <905000 905000 1140000>; 192 opp-supported-hw = <0x7>; 193 clock-latency-ns = <200000>; 194 required-opps = <&cpr_opp1>; 195 }; 196 opp-1401600000 { 197 opp-hz = /bits/ 64 <1401600000>; 198 opp-microvolt = <1140000 905000 1140000>; 199 opp-supported-hw = <0x5>; 200 clock-latency-ns = <200000>; 201 required-opps = <&cpr_opp2>; 202 }; 203 opp-1593600000 { 204 opp-hz = /bits/ 64 <1593600000>; 205 opp-microvolt = <1140000 905000 1140000>; 206 opp-supported-hw = <0x1>; 207 clock-latency-ns = <200000>; 208 required-opps = <&cpr_opp3>; 209 }; 210 }; 211 212 cluster1_opp: opp-table-1 { 213 compatible = "operating-points-v2-kryo-cpu"; 214 nvmem-cells = <&speedbin_efuse>; 215 opp-shared; 216 217 opp-307200000 { 218 opp-hz = /bits/ 64 <307200000>; 219 opp-microvolt = <905000 905000 1140000>; 220 opp-supported-hw = <0x7>; 221 clock-latency-ns = <200000>; 222 required-opps = <&cpr_opp1>; 223 }; 224 opp-1804800000 { 225 opp-hz = /bits/ 64 <1804800000>; 226 opp-microvolt = <1140000 905000 1140000>; 227 opp-supported-hw = <0x6>; 228 clock-latency-ns = <200000>; 229 required-opps = <&cpr_opp4>; 230 }; 231 opp-1900800000 { 232 opp-hz = /bits/ 64 <1900800000>; 233 opp-microvolt = <1140000 905000 1140000>; 234 opp-supported-hw = <0x4>; 235 clock-latency-ns = <200000>; 236 required-opps = <&cpr_opp5>; 237 }; 238 opp-2150400000 { 239 opp-hz = /bits/ 64 <2150400000>; 240 opp-microvolt = <1140000 905000 1140000>; 241 opp-supported-hw = <0x1>; 242 clock-latency-ns = <200000>; 243 required-opps = <&cpr_opp6>; 244 }; 245 }; 246 247 smem { 248 compatible = "qcom,smem"; 249 memory-region = <&smem_mem>; 250 hwlocks = <&tcsr_mutex 3>; 251 }; 252 253 soc { 254 #address-cells = <1>; 255 #size-cells = <1>; 256 257 qfprom: qfprom@74000 { 258 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 259 reg = <0x00074000 0x8ff>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 263 speedbin_efuse: speedbin@133 { 264 reg = <0x133 0x1>; 265 bits = <5 3>; 266 }; 267 }; 268 }; 269 }; 270