1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/nvmem/nvmem.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVMEM (Non Volatile Memory) Device Tree Bindings 8 9maintainers: 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11 12description: | 13 This binding is intended to represent the location of hardware 14 configuration data stored in NVMEMs like eeprom, efuses and so on. 15 16 On a significant proportion of boards, the manufacturer has stored 17 some data on NVMEM, for the OS to be able to retrieve these 18 information and act upon it. Obviously, the OS has to know about 19 where to retrieve these data from, and where they are stored on the 20 storage device. 21 22properties: 23 $nodename: 24 pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$" 25 26 "#address-cells": 27 const: 1 28 29 "#size-cells": 30 const: 1 31 32 read-only: 33 $ref: /schemas/types.yaml#/definitions/flag 34 description: 35 Mark the provider as read only. 36 37 wp-gpios: 38 description: 39 GPIO to which the write-protect pin of the chip is connected. 40 The write-protect GPIO is asserted, when it's driven high 41 (logical '1') to block the write operation. It's deasserted, 42 when it's driven low (logical '0') to allow writing. 43 maxItems: 1 44 45patternProperties: 46 "^.*@[0-9a-f]+$": 47 type: object 48 49 properties: 50 reg: 51 maxItems: 1 52 description: 53 Offset and size in bytes within the storage device. 54 55 bits: 56 maxItems: 1 57 items: 58 items: 59 - minimum: 0 60 maximum: 7 61 description: 62 Offset in bit within the address range specified by reg. 63 - minimum: 1 64 description: 65 Size in bit within the address range specified by reg. 66 67 required: 68 - reg 69 70additionalProperties: true 71 72examples: 73 - | 74 #include <dt-bindings/gpio/gpio.h> 75 76 qfprom: eeprom@700000 { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 reg = <0x00700000 0x100000>; 80 81 wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 82 83 /* ... */ 84 85 /* Data cells */ 86 tsens_calibration: calib@404 { 87 reg = <0x404 0x10>; 88 }; 89 90 tsens_calibration_bckp: calib_bckp@504 { 91 reg = <0x504 0x11>; 92 bits = <6 128>; 93 }; 94 95 pvs_version: pvs-version@6 { 96 reg = <0x6 0x2>; 97 bits = <7 2>; 98 }; 99 100 speed_bin: speed-bin@c{ 101 reg = <0xc 0x1>; 102 bits = <2 3>; 103 }; 104 }; 105 106... 107