1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/nvmem/nvmem.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVMEM (Non Volatile Memory) 8 9maintainers: 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11 12description: | 13 This binding is intended to represent the location of hardware 14 configuration data stored in NVMEMs like eeprom, efuses and so on. 15 16 On a significant proportion of boards, the manufacturer has stored 17 some data on NVMEM, for the OS to be able to retrieve these 18 information and act upon it. Obviously, the OS has to know about 19 where to retrieve these data from, and where they are stored on the 20 storage device. 21 22properties: 23 "#address-cells": 24 const: 1 25 26 "#size-cells": 27 const: 1 28 29 read-only: 30 $ref: /schemas/types.yaml#/definitions/flag 31 description: 32 Mark the provider as read only. 33 34 wp-gpios: 35 description: 36 GPIO to which the write-protect pin of the chip is connected. 37 The write-protect GPIO is asserted, when it's driven high 38 (logical '1') to block the write operation. It's deasserted, 39 when it's driven low (logical '0') to allow writing. 40 maxItems: 1 41 42 nvmem-layout: 43 $ref: /schemas/nvmem/layouts/nvmem-layout.yaml 44 description: 45 Alternative to the statically defined nvmem cells, this 46 container may reference more advanced (dynamic) layout 47 parsers. 48 49patternProperties: 50 "@[0-9a-f]+(,[0-7])?$": 51 type: object 52 $ref: layouts/fixed-cell.yaml 53 deprecated: true 54 55additionalProperties: true 56 57examples: 58 - | 59 #include <dt-bindings/gpio/gpio.h> 60 61 qfprom: eeprom@700000 { 62 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 reg = <0x00700000 0x100000>; 66 67 wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 68 69 /* ... */ 70 71 nvmem-layout { 72 compatible = "fixed-layout"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 76 /* Data cells */ 77 tsens_calibration: calib@404 { 78 reg = <0x404 0x10>; 79 }; 80 81 tsens_calibration_bckp: calib_bckp@504 { 82 reg = <0x504 0x11>; 83 bits = <6 128>; 84 }; 85 86 pvs_version: pvs-version@6 { 87 reg = <0x6 0x2>; 88 bits = <7 2>; 89 }; 90 91 speed_bin: speed-bin@c{ 92 reg = <0xc 0x1>; 93 bits = <2 3>; 94 }; 95 }; 96 }; 97 98... 99